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Searched refs:reg_vals (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.c12 …c_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);
126 return dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, &dsc_optc_cfg); in dsc401_validate_stream()
137 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, dsc_optc_cfg); in dsc401_set_config()
140 dsc_log_pps(dsc, &dsc401->reg_vals.pps); in dsc401_set_config()
141 dsc_write_to_registers(dsc, &dsc401->reg_vals); in dsc401_set_config()
205 …sc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals) in dsc_write_to_registers() argument
211 DSC_DBG_EN, reg_vals->dsc_dbg_en); in dsc_write_to_registers()
218 INPUT_PIXEL_FORMAT, reg_vals->pixel_format, in dsc_write_to_registers()
219 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); in dsc_write_to_registers()
228 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, in dsc_write_to_registers()
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H A Ddcn401_dsc.h323 struct dsc_reg_values reg_vals; member
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
H A Ddcn20_dsc.c33 …c_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);
175 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); in dsc2_validate_stream()
198 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg); in dsc2_set_config()
201 dsc_log_pps(dsc, &dsc20->reg_vals.pps); in dsc2_set_config()
202 dsc_write_to_registers(dsc, &dsc20->reg_vals); in dsc2_set_config()
517 void dsc_init_reg_values(struct dsc_reg_values *reg_vals) in dsc_init_reg_values() argument
521 memset(reg_vals, 0, sizeof(struct dsc_reg_values)); in dsc_init_reg_values()
524 reg_vals->dsc_clock_enable = 1; in dsc_init_reg_values()
525 reg_vals->dsc_clock_gating_disable = 0; in dsc_init_reg_values()
526 reg_vals->underflow_recovery_en = 0; in dsc_init_reg_values()
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/linux/drivers/net/ethernet/intel/idpf/
H A Didpf_vf_dev.c79 struct idpf_vec_regs *reg_vals; in idpf_vf_intr_reg_init() local
85 reg_vals = kzalloc_objs(struct idpf_vec_regs, total_vecs); in idpf_vf_intr_reg_init()
86 if (!reg_vals) in idpf_vf_intr_reg_init()
89 num_regs = idpf_get_reg_intr_vecs(adapter, reg_vals); in idpf_vf_intr_reg_init()
102 reg_vals[vec_id].dyn_ctl_reg); in idpf_vf_intr_reg_init()
112 spacing = IDPF_ITR_IDX_SPACING(reg_vals[vec_id].itrn_index_spacing, in idpf_vf_intr_reg_init()
115 reg_vals[vec_id].itrn_reg, in idpf_vf_intr_reg_init()
118 reg_vals[vec_id].itrn_reg, in idpf_vf_intr_reg_init()
126 val = reg_vals[rsrc->q_vector_idxs[i] - IDPF_MBX_Q_VEC].dyn_ctl_reg; in idpf_vf_intr_reg_init()
134 kfree(reg_vals); in idpf_vf_intr_reg_init()
H A Didpf_dev.c80 struct idpf_vec_regs *reg_vals; in idpf_intr_reg_init() local
86 reg_vals = kzalloc_objs(struct idpf_vec_regs, total_vecs); in idpf_intr_reg_init()
87 if (!reg_vals) in idpf_intr_reg_init()
90 num_regs = idpf_get_reg_intr_vecs(adapter, reg_vals); in idpf_intr_reg_init()
103 reg_vals[vec_id].dyn_ctl_reg); in idpf_intr_reg_init()
113 spacing = IDPF_ITR_IDX_SPACING(reg_vals[vec_id].itrn_index_spacing, in idpf_intr_reg_init()
116 reg_vals[vec_id].itrn_reg, in idpf_intr_reg_init()
119 reg_vals[vec_id].itrn_reg, in idpf_intr_reg_init()
127 val = reg_vals[rsrc->q_vector_idxs[i] - IDPF_MBX_Q_VEC].dyn_ctl_reg; in idpf_intr_reg_init()
135 kfree(reg_vals); in idpf_intr_reg_init()
H A Didpf_virtchnl.c1325 struct idpf_vec_regs *reg_vals) in idpf_get_reg_intr_vecs() argument
1350 reg_vals[num_regs].dyn_ctl_reg = reg_val.dyn_ctl_reg; in idpf_get_reg_intr_vecs()
1351 reg_vals[num_regs].itrn_reg = reg_val.itrn_reg; in idpf_get_reg_intr_vecs()
1352 reg_vals[num_regs].itrn_index_spacing = in idpf_get_reg_intr_vecs()
1376 static int idpf_vport_get_q_reg(u32 *reg_vals, int num_regs, u32 q_type, in idpf_vport_get_q_reg() argument
1394 reg_vals[reg_filled++] = reg_val; in idpf_vport_get_q_reg()
1413 struct idpf_q_vec_rsrc *rsrc, u32 *reg_vals, in __idpf_queue_reg_init() argument
1426 idpf_get_reg_addr(adapter, reg_vals[k]); in __idpf_queue_reg_init()
1439 reg_vals[k]); in __idpf_queue_reg_init()
1453 reg_vals[k]); in __idpf_queue_reg_init()
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H A Didpf_virtchnl.h107 struct idpf_vec_regs *reg_vals);
/linux/drivers/media/dvb-frontends/
H A Dts2020.c95 static const struct ts2020_reg_val reg_vals[] = { in ts2020_init() local
137 for (i = 0; i < ARRAY_SIZE(reg_vals); i++) in ts2020_init()
138 regmap_write(priv->regmap, reg_vals[i].reg, in ts2020_init()
139 reg_vals[i].val); in ts2020_init()
/linux/drivers/media/tuners/
H A Dm88rs6000t.c587 static const struct m88rs6000t_reg_val reg_vals[] = { in m88rs6000t_probe() local
679 for (i = 0; i < ARRAY_SIZE(reg_vals); i++) { in m88rs6000t_probe()
681 reg_vals[i].reg, reg_vals[i].val); in m88rs6000t_probe()
/linux/sound/soc/codecs/
H A Dcs48l32.c1338 u32 reg_vals[4]; in cs48l32_irq() local
1345 static_assert(ARRAY_SIZE(eint1_regs) == ARRAY_SIZE(reg_vals)); in cs48l32_irq()
1361 ret = regmap_multi_reg_read(regmap, eint1_regs, reg_vals, ARRAY_SIZE(reg_vals)); in cs48l32_irq()
1367 for (i = 0; i < ARRAY_SIZE(reg_vals); i += 2) { in cs48l32_irq()
1368 reg_vals[i] &= ~reg_vals[i + 1]; in cs48l32_irq()
1369 regmap_write(regmap, eint1_regs[i], reg_vals[i]); in cs48l32_irq()
1372 if (reg_vals[0] & CS48L32_DSP1_IRQ0_EINT1_MASK) in cs48l32_irq()
1375 if (reg_vals[ in cs48l32_irq()
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