Searched refs:reg_val_offs (Results 1 – 8 of 8) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_gfx.c | 1228 uint32_t seq, reg_val_offs = 0, value = 0; in amdgpu_kiq_rreg() local
1241 if (amdgpu_wb_get(adev, ®_val_offs)) { in amdgpu_kiq_rreg()
1249 amdgpu_ring_emit_rreg(ring, reg, reg_val_offs); in amdgpu_kiq_rreg()
1283 value = adev->wb.wb[reg_val_offs]; in amdgpu_kiq_rreg()
1284 amdgpu_wb_free(adev, reg_val_offs); in amdgpu_kiq_rreg()
1292 if (reg_val_offs) in amdgpu_kiq_rreg()
1293 amdgpu_wb_free(adev, reg_val_offs); in amdgpu_kiq_rreg()
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| H A D | gfx_v9_0.c | 4263 uint32_t seq, reg_val_offs = 0; in gfx_v9_0_kiq_read_clock() local
4271 if (amdgpu_wb_get(adev, ®_val_offs)) { in gfx_v9_0_kiq_read_clock()
4284 reg_val_offs * 4)); in gfx_v9_0_kiq_read_clock()
4286 reg_val_offs * 4)); in gfx_v9_0_kiq_read_clock()
4317 value = (uint64_t)adev->wb.wb[reg_val_offs] | in gfx_v9_0_kiq_read_clock()
4318 (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL; in gfx_v9_0_kiq_read_clock()
4319 amdgpu_wb_free(adev, reg_val_offs); in gfx_v9_0_kiq_read_clock()
4327 if (reg_val_offs) in gfx_v9_0_kiq_read_clock()
4328 amdgpu_wb_free(adev, reg_val_offs); in gfx_v9_0_kiq_read_clock()
5928 uint32_t reg_val_offs) in gfx_v9_0_ring_emit_rreg() argument
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| H A D | gfx_v9_4_3.c | 3096 uint32_t reg_val_offs) in gfx_v9_4_3_ring_emit_rreg() argument
3109 reg_val_offs * 4)); in gfx_v9_4_3_ring_emit_rreg()
3111 reg_val_offs * 4)); in gfx_v9_4_3_ring_emit_rreg()
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| H A D | gfx_v12_1.c | 3828 uint32_t reg_val_offs) in gfx_v12_1_ring_emit_rreg() argument
3841 reg_val_offs * 4)); in gfx_v12_1_ring_emit_rreg()
3843 reg_val_offs * 4)); in gfx_v12_1_ring_emit_rreg()
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| H A D | gfx_v12_0.c | 4693 uint32_t reg_val_offs) in gfx_v12_0_ring_emit_rreg() argument
4704 reg_val_offs * 4)); in gfx_v12_0_ring_emit_rreg()
4706 reg_val_offs * 4)); in gfx_v12_0_ring_emit_rreg()
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| H A D | gfx_v8_0.c | 6239 uint32_t reg_val_offs) in gfx_v8_0_ring_emit_rreg() argument
6250 reg_val_offs * 4)); in gfx_v8_0_ring_emit_rreg()
6252 reg_val_offs * 4)); in gfx_v8_0_ring_emit_rreg()
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| H A D | gfx_v11_0.c | 6348 uint32_t reg_val_offs) in gfx_v11_0_ring_emit_rreg() argument
6359 reg_val_offs * 4)); in gfx_v11_0_ring_emit_rreg()
6361 reg_val_offs * 4)); in gfx_v11_0_ring_emit_rreg()
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| H A D | gfx_v10_0.c | 8993 uint32_t reg_val_offs) in gfx_v10_0_ring_emit_rreg() argument
9004 reg_val_offs * 4)); in gfx_v10_0_ring_emit_rreg()
9006 reg_val_offs * 4)); in gfx_v10_0_ring_emit_rreg()
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