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Searched refs:reg_val (Results 1 – 25 of 279) sorted by relevance

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/linux/drivers/input/keyboard/
H A Dimx_keypad.c83 unsigned short reg_val; in imx_keypad_scan_matrix() local
94 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
95 reg_val |= 0xff00; in imx_keypad_scan_matrix()
96 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
98 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
99 reg_val &= ~((keypad->cols_en_mask & 0xff) << 8); in imx_keypad_scan_matrix()
100 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
104 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
105 reg_val |= (keypad->cols_en_mask & 0xff) << 8; in imx_keypad_scan_matrix()
106 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
[all …]
/linux/drivers/media/dvb-frontends/
H A Daf9033_priv.h19 struct reg_val { struct
87 static const struct reg_val ofsm_init[] = {
202 static const struct reg_val tuner_init_tua9001[] = {
246 static const struct reg_val tuner_init_fc0011[] = {
309 static const struct reg_val tuner_init_fc0012[] = {
354 static const struct reg_val tuner_init_mxl5007t[] = {
391 static const struct reg_val tuner_init_tda18218[] = {
427 static const struct reg_val tuner_init_fc2580[] = {
467 static const struct reg_val ofsm_init_it9135_v1[] = {
582 static const struct reg_val tuner_init_it9135_38[] = {
[all …]
/linux/drivers/spi/
H A Dspi-mt65xx.c286 u32 reg_val; in mtk_spi_reset() local
289 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
290 reg_val |= SPI_CMD_RST; in mtk_spi_reset()
291 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
293 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
294 reg_val &= ~SPI_CMD_RST; in mtk_spi_reset()
295 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
305 u32 reg_val; in mtk_spi_set_hw_cs_timing() local
324 reg_val = readl(mdata->base + SPI_CFG0_REG); in mtk_spi_set_hw_cs_timing()
328 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
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/linux/drivers/net/ethernet/allwinner/
H A Dsun4i-emac.c105 unsigned int reg_val; in emac_update_speed() local
108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
109 reg_val &= ~EMAC_MAC_SUPP_100M; in emac_update_speed()
111 reg_val |= EMAC_MAC_SUPP_100M; in emac_update_speed()
112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
118 unsigned int reg_val; in emac_update_duplex() local
121 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
122 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
124 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
125 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
[all …]
/linux/sound/drivers/opl3/
H A Dopl3_synth.c394 unsigned char reg_val; in snd_opl3_play_note() local
414 reg_val = (unsigned char) note->fnum; in snd_opl3_play_note()
416 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note()
418 reg_val = 0x00; in snd_opl3_play_note()
421 reg_val |= OPL3_KEYON_BIT; in snd_opl3_play_note()
423 reg_val |= (note->octave << 2) & OPL3_BLOCKNUM_MASK; in snd_opl3_play_note()
425 reg_val |= (unsigned char) (note->fnum >> 8) & OPL3_FNUM_HIGH_MASK; in snd_opl3_play_note()
429 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note()
442 unsigned char reg_val; in snd_opl3_set_voice() local
468 reg_val = 0x00; in snd_opl3_set_voice()
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/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_hdcp.c45 u32 reg_val; member
199 u32 reg_val, hdcp_int_status; in msm_hdmi_hdcp_irq() local
203 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL); in msm_hdmi_hdcp_irq()
204 hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK; in msm_hdmi_hdcp_irq()
210 reg_val |= hdcp_int_status << 1; in msm_hdmi_hdcp_irq()
213 reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK; in msm_hdmi_hdcp_irq()
214 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val); in msm_hdmi_hdcp_irq()
228 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); in msm_hdmi_hdcp_irq()
230 __func__, reg_val); in msm_hdmi_hdcp_irq()
284 u32 reg_val, failure, nack0; in msm_reset_hdcp_ddc_failures() local
[all …]
/linux/arch/arm/mach-qcom/
H A Dplatsmp.c84 u32 reg_val; in cortex_a7_release_secondary() local
103 reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP; in cortex_a7_release_secondary()
104 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
111 reg_val &= ~CORE_MEM_CLAMP; in cortex_a7_release_secondary()
112 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
113 reg_val |= L2DT_SLP; in cortex_a7_release_secondary()
114 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
117 reg_val = (reg_val | BIT(17)) & ~CLAMP; in cortex_a7_release_secondary()
118 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
122 reg_val &= ~(CORE_RST | COREPOR_RST); in cortex_a7_release_secondary()
[all …]
/linux/drivers/hwmon/
H A Dltc2992.c420 int reg_val; in ltc2992_get_voltage() local
422 reg_val = ltc2992_read_reg(st, reg, 2); in ltc2992_get_voltage()
423 if (reg_val < 0) in ltc2992_get_voltage()
424 return reg_val; in ltc2992_get_voltage()
426 reg_val = reg_val >> 4; in ltc2992_get_voltage()
427 *val = DIV_ROUND_CLOSEST(reg_val * scale, 1000); in ltc2992_get_voltage()
442 int reg_val; in ltc2992_read_gpio_alarm() local
450 reg_val = ltc2992_read_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1); in ltc2992_read_gpio_alarm()
451 if (reg_val < 0) in ltc2992_read_gpio_alarm()
452 return reg_val; in ltc2992_read_gpio_alarm()
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn23xx_vf_device.c68 u64 reg_val = octeon_read_csr64(oct, in cn23xx_vf_reset_io_queues() local
70 while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) && in cn23xx_vf_reset_io_queues()
71 !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) && in cn23xx_vf_reset_io_queues()
73 WRITE_ONCE(reg_val, octeon_read_csr64( in cn23xx_vf_reset_io_queues()
83 WRITE_ONCE(reg_val, READ_ONCE(reg_val) & in cn23xx_vf_reset_io_queues()
86 READ_ONCE(reg_val)); in cn23xx_vf_reset_io_queues()
88 WRITE_ONCE(reg_val, octeon_read_csr64( in cn23xx_vf_reset_io_queues()
90 if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) { in cn23xx_vf_reset_io_queues()
153 u32 reg_val; in cn23xx_vf_setup_global_output_regs() local
160 reg_val = in cn23xx_vf_setup_global_output_regs()
[all …]
H A Dcn23xx_pf_device.c136 u64 reg_val; in cn23xx_setup_global_mac_regs() local
145 reg_val = in cn23xx_setup_global_mac_regs()
150 reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF_PASS_1_1; in cn23xx_setup_global_mac_regs()
153 reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF; in cn23xx_setup_global_mac_regs()
157 reg_val = reg_val | in cn23xx_setup_global_mac_regs()
161 reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_RPVF_BIT_POS); in cn23xx_setup_global_mac_regs()
165 reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_NVFS_BIT_POS); in cn23xx_setup_global_mac_regs()
169 reg_val); in cn23xx_setup_global_mac_regs()
199 u64 reg_val = octeon_read_csr64(oct, in cn23xx_reset_io_queues() local
201 while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) && in cn23xx_reset_io_queues()
[all …]
/linux/arch/powerpc/platforms/powernv/
H A Dopal-fadump.h83 __be64 reg_val; member
88 u64 reg_val) in opal_fadump_set_regval_regnum() argument
92 regs->gpr[reg_num] = reg_val; in opal_fadump_set_regval_regnum()
98 regs->ctr = reg_val; in opal_fadump_set_regval_regnum()
101 regs->link = reg_val; in opal_fadump_set_regval_regnum()
104 regs->xer = reg_val; in opal_fadump_set_regval_regnum()
107 regs->dar = reg_val; in opal_fadump_set_regval_regnum()
110 regs->dsisr = reg_val; in opal_fadump_set_regval_regnum()
113 regs->nip = reg_val; in opal_fadump_set_regval_regnum()
116 regs->msr = reg_val; in opal_fadump_set_regval_regnum()
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/linux/arch/mips/pci/
H A Dfixup-malta.c70 unsigned char reg_val; in malta_piix_func0_fixup() local
84 pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, &reg_val); in malta_piix_func0_fixup()
85 if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE) in malta_piix_func0_fixup()
88 pci_irq[PCIA+i] = piixirqmap[reg_val & in malta_piix_func0_fixup()
98 pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val); in malta_piix_func0_fixup()
99 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | in malta_piix_func0_fixup()
109 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val); in malta_piix_func0_fixup()
110 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT; in malta_piix_func0_fixup()
111 pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val); in malta_piix_func0_fixup()
124 unsigned char reg_val; in malta_piix_func1_fixup() local
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/linux/drivers/staging/media/starfive/camss/
H A Dstf-isp-hw-ops.c15 u32 reg_val, reg_add; in stf_isp_config_obc() local
19 reg_val = GAIN_D_POINT(0x40) | GAIN_C_POINT(0x40) | in stf_isp_config_obc()
22 stf_isp_reg_write(stfcamss, reg_add, reg_val); in stf_isp_config_obc()
26 reg_val = OFFSET_D_POINT(0) | OFFSET_C_POINT(0) | in stf_isp_config_obc()
29 stf_isp_reg_write(stfcamss, reg_add, reg_val); in stf_isp_config_obc()
120 u32 reg_val, reg_add; in stf_isp_config_awb() local
124 reg_val = AWB_X_SYMBOL_H(symbol_h) | AWB_X_SYMBOL_L(symbol_l); in stf_isp_config_awb()
127 stf_isp_reg_write(stfcamss, reg_add, reg_val); in stf_isp_config_awb()
132 reg_val = AWB_Y_SYMBOL_H(symbol_h) | AWB_Y_SYMBOL_L(symbol_l); in stf_isp_config_awb()
135 stf_isp_reg_write(stfcamss, reg_add, reg_val); in stf_isp_config_awb()
[all …]
/linux/drivers/video/backlight/
H A Dlm3639_bl.c50 unsigned int reg_val; in lm3639_chip_init() local
60 reg_val = (pdata->pin_pwm & 0x40) | pdata->pin_strobe | pdata->pin_tx; in lm3639_chip_init()
61 ret = regmap_update_bits(pchip->regmap, REG_IO_CTRL, 0x7C, reg_val); in lm3639_chip_init()
76 reg_val = pdata->fled_pins; in lm3639_chip_init()
77 reg_val |= pdata->bled_pins; in lm3639_chip_init()
79 reg_val = pdata->fled_pins; in lm3639_chip_init()
80 reg_val |= pdata->bled_pins | 0x01; in lm3639_chip_init()
83 ret = regmap_update_bits(pchip->regmap, REG_ENABLE, 0x79, reg_val); in lm3639_chip_init()
97 unsigned int reg_val; in lm3639_bled_update_status() local
101 ret = regmap_read(pchip->regmap, REG_FLAG, &reg_val); in lm3639_bled_update_status()
[all …]
/linux/drivers/power/supply/
H A Dintel_dc_ti_battery.c132 unsigned int reg_val; in dc_ti_battery_get_voltage_and_current_now() local
165 ret = regmap_read(chip->regmap, DC_TI_CC_ACC0_REG, &reg_val); in dc_ti_battery_get_voltage_and_current_now()
169 acc = reg_val; in dc_ti_battery_get_voltage_and_current_now()
171 ret = regmap_read(chip->regmap, DC_TI_CC_ACC1_REG, &reg_val); in dc_ti_battery_get_voltage_and_current_now()
175 acc |= reg_val << 8; in dc_ti_battery_get_voltage_and_current_now()
177 ret = regmap_read(chip->regmap, DC_TI_CC_ACC2_REG, &reg_val); in dc_ti_battery_get_voltage_and_current_now()
181 acc |= reg_val << 16; in dc_ti_battery_get_voltage_and_current_now()
183 ret = regmap_read(chip->regmap, DC_TI_CC_ACC3_REG, &reg_val); in dc_ti_battery_get_voltage_and_current_now()
187 acc |= reg_val << 24; in dc_ti_battery_get_voltage_and_current_now()
190 ret = regmap_read(chip->regmap, DC_TI_SMPL_CTR0_REG, &reg_val); in dc_ti_battery_get_voltage_and_current_now()
[all …]
H A Dmax1720x_battery.c366 unsigned int reg_val; in max1720x_battery_get_property() local
371 ret = max172xx_battery_health(info, &reg_val); in max1720x_battery_get_property()
372 val->intval = reg_val; in max1720x_battery_get_property()
380 ret = regmap_read(info->regmap, MAX172XX_STATUS, &reg_val); in max1720x_battery_get_property()
386 val->intval = !FIELD_GET(MAX172XX_STATUS_BAT_ABSENT, reg_val); in max1720x_battery_get_property()
389 ret = regmap_read(info->regmap, MAX172XX_REPSOC, &reg_val); in max1720x_battery_get_property()
390 val->intval = max172xx_percent_to_ps(reg_val); in max1720x_battery_get_property()
393 ret = regmap_read(info->regmap, MAX172XX_BATT, &reg_val); in max1720x_battery_get_property()
394 val->intval = max172xx_voltage_to_ps(reg_val); in max1720x_battery_get_property()
397 ret = regmap_read(info->regmap, MAX172XX_DESIGN_CAP, &reg_val); in max1720x_battery_get_property()
[all …]
/linux/sound/soc/codecs/aw88395/
H A Daw88395_device.c190 int reg_val; in aw_dev_read_chipid()
193 ret = regmap_read(aw_dev->regmap, AW88395_CHIP_ID_REG, &reg_val); in aw_dev_read_chipid()
199 dev_info(aw_dev->dev, "chip id = %x\n", reg_val); in aw_dev_read_chipid()
200 *chip_id = reg_val; in aw_dev_read_chipid()
452 unsigned int reg_val; in aw_dev_dsp_check_st()
457 ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, &reg_val); in aw_dev_dsp_check_st()
463 if ((reg_val & (~AW88395_DSPS_MASK)) != AW88395_DSPS_NORMAL_VALUE) { in aw_dev_dsp_check_st()
464 dev_err(aw_dev->dev, "check dsp st fail,reg_val:0x%04x", reg_val); in aw_dev_dsp_check_st()
468 dev_dbg(aw_dev->dev, "dsp st check ok, reg_val in aw_dev_dsp_check_st()
189 int reg_val; aw_dev_read_chipid() local
451 unsigned int reg_val; aw_dev_dsp_check_st() local
575 unsigned int reg_val; aw_dev_get_icalk() local
595 unsigned int reg_val; aw_dev_get_vcalk() local
617 unsigned int reg_val; aw_dev_get_vcalk_dac() local
662 u32 vcalb_adj, reg_val; aw_dev_set_vcalb() local
757 unsigned int reg_val; aw_dev_get_int_status() local
783 unsigned int reg_val; aw_dev_get_iis_status() local
816 unsigned int reg_val; aw_dev_check_mode2_pll() local
884 unsigned int reg_val; aw_dev_check_sysst() local
908 u16 reg_val; aw_dev_check_sysint() local
923 unsigned int reg_val; aw_dev_get_cur_mode_st() local
939 unsigned int reg_val = 0; aw_dev_get_dsp_config() local
980 unsigned int reg_val; aw_dev_get_dsp_status() local
1005 u16 reg_val; aw_dev_update_reg_container() local
1126 __be16 reg_val; aw_dev_dsp_update_container() local
1231 unsigned int reg_val; aw_dev_check_sram() local
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/linux/arch/riscv/kvm/
H A Dvcpu_sbi.c220 unsigned long reg_val) in riscv_vcpu_set_sbi_ext_single() argument
225 if (reg_val != 1 && reg_val != 0) in riscv_vcpu_set_sbi_ext_single()
232 scontext->ext_status[sext->ext_idx] = (reg_val) ? in riscv_vcpu_set_sbi_ext_single()
241 unsigned long *reg_val) in riscv_vcpu_get_sbi_ext_single() argument
250 *reg_val = scontext->ext_status[sext->ext_idx] == in riscv_vcpu_get_sbi_ext_single()
258 unsigned long reg_val, bool enable) in riscv_vcpu_set_sbi_ext_multi() argument
265 for_each_set_bit(i, &reg_val, BITS_PER_LONG) { in riscv_vcpu_set_sbi_ext_multi()
278 unsigned long *reg_val) in riscv_vcpu_get_sbi_ext_multi() argument
293 *reg_val |= KVM_REG_RISCV_SBI_MULTI_MASK(ext_id); in riscv_vcpu_get_sbi_ext_multi()
332 unsigned long reg_val, reg_subtype; in kvm_riscv_vcpu_set_reg_sbi_ext() local
[all …]
/linux/drivers/media/i2c/
H A Dlm3646.c102 unsigned int reg_val; in lm3646_get_ctrl() local
108 rval = regmap_read(flash->regmap, REG_FLAG, &reg_val); in lm3646_get_ctrl()
113 if (reg_val & FAULT_TIMEOUT) in lm3646_get_ctrl()
115 if (reg_val & FAULT_SHORT_CIRCUIT) in lm3646_get_ctrl()
117 if (reg_val & FAULT_UVLO) in lm3646_get_ctrl()
119 if (reg_val & FAULT_IVFM) in lm3646_get_ctrl()
121 if (reg_val & FAULT_OCP) in lm3646_get_ctrl()
123 if (reg_val & FAULT_OVERTEMP) in lm3646_get_ctrl()
125 if (reg_val & FAULT_NTC_TRIP) in lm3646_get_ctrl()
127 if (reg_val & FAULT_OVP) in lm3646_get_ctrl()
[all …]
/linux/drivers/edac/
H A Ddmc520_edac.c255 u32 reg_val = readl(reg_base + REG_OFFSET_FEATURE_CONFIG); in dmc520_is_ecc_enabled() local
257 return FIELD_GET(REG_FIELD_DRAM_ECC_ENABLED, reg_val); in dmc520_is_ecc_enabled()
263 u32 reg_val, scrub_cfg; in dmc520_get_scrub_type() local
265 reg_val = dmc520_read_reg(pvt, REG_OFFSET_SCRUB_CONTROL0_NOW); in dmc520_get_scrub_type()
266 scrub_cfg = FIELD_GET(SCRUB_TRIGGER0_NEXT_MASK, reg_val); in dmc520_get_scrub_type()
280 u32 reg_val; in dmc520_get_memory_width() local
282 reg_val = dmc520_read_reg(pvt, REG_OFFSET_FORMAT_CONTROL); in dmc520_get_memory_width()
283 mem_width_field = FIELD_GET(MEMORY_WIDTH_MASK, reg_val); in dmc520_get_memory_width()
296 u32 reg_val; in dmc520_get_mtype() local
298 reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW); in dmc520_get_mtype()
[all …]
/linux/drivers/mtd/nand/raw/
H A Domap_elm.c106 u32 reg_val; in elm_config() local
124 reg_val = (bch_type & ECC_BCH_LEVEL_MASK) | (ELM_ECC_SIZE << 16); in elm_config()
125 elm_write_reg(info, ELM_LOCATION_CONFIG, reg_val); in elm_config()
145 u32 reg_val; in elm_configure_page_mode() local
147 reg_val = elm_read_reg(info, ELM_PAGE_CTRL); in elm_configure_page_mode()
149 reg_val |= BIT(index); /* enable page mode */ in elm_configure_page_mode()
151 reg_val &= ~BIT(index); /* disable page mode */ in elm_configure_page_mode()
153 elm_write_reg(info, ELM_PAGE_CTRL, reg_val); in elm_configure_page_mode()
254 u32 reg_val; in elm_start_processing() local
264 reg_val = elm_read_reg(info, offset); in elm_start_processing()
[all …]
/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.c76 uint32_t reg_val; in dmub_reg_update() local
84 reg_val = srv->funcs.reg_read(srv->user_ctx, addr); in dmub_reg_update()
85 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in dmub_reg_update()
86 srv->funcs.reg_write(srv->user_ctx, addr, reg_val); in dmub_reg_update()
89 void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n, in dmub_reg_set() argument
100 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in dmub_reg_set()
101 srv->funcs.reg_write(srv->user_ctx, addr, reg_val); in dmub_reg_set()
107 uint32_t reg_val = srv->funcs.reg_read(srv->user_ctx, addr); in dmub_reg_get() local
108 *field_value = get_reg_field_value_ex(reg_val, mask, shift); in dmub_reg_get()
/linux/drivers/net/wireless/ath/ath10k/
H A Dhw.c746 u32 addr, reg_val, mem_val; in ath10k_hw_qca6174_enable_pll_clock() local
763 ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val); in ath10k_hw_qca6174_enable_pll_clock()
768 if (MS(reg_val, EFUSE_XTAL_SEL) > ATH10K_HW_REFCLK_COUNT) in ath10k_hw_qca6174_enable_pll_clock()
771 hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)]; in ath10k_hw_qca6174_enable_pll_clock()
775 ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val); in ath10k_hw_qca6174_enable_pll_clock()
779 reg_val &= ~(BB_PLL_CONFIG_FRAC_MASK | BB_PLL_CONFIG_OUTDIV_MASK); in ath10k_hw_qca6174_enable_pll_clock()
780 reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) | in ath10k_hw_qca6174_enable_pll_clock()
782 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); in ath10k_hw_qca6174_enable_pll_clock()
788 ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val); in ath10k_hw_qca6174_enable_pll_clock()
792 reg_val &= ~WLAN_PLL_SETTLE_TIME_MASK; in ath10k_hw_qca6174_enable_pll_clock()
[all …]
/linux/arch/x86/hyperv/
H A Dhv_apic.c39 u64 reg_val; in hv_apic_icr_read() local
41 rdmsrq(HV_X64_MSR_ICR, reg_val); in hv_apic_icr_read()
42 return reg_val; in hv_apic_icr_read()
47 u64 reg_val; in hv_apic_icr_write() local
49 reg_val = SET_XAPIC_DEST_FIELD(id); in hv_apic_icr_write()
50 reg_val = reg_val << 32; in hv_apic_icr_write()
51 reg_val |= low; in hv_apic_icr_write()
53 wrmsrq(HV_X64_MSR_ICR, reg_val); in hv_apic_icr_write()
63 u32 reg_val, hi; in hv_apic_read() local
67 rdmsr(HV_X64_MSR_EOI, reg_val, hi); in hv_apic_read()
[all …]
/linux/drivers/clk/bcm/
H A Dclk-kona.c35 static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width) in bitfield_extract() argument
37 return (reg_val & bitfield_mask(shift, width)) >> shift; in bitfield_extract()
41 static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val) in bitfield_replace() argument
45 return (reg_val & ~mask) | (val << shift); in bitfield_replace()
112 __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val) in __ccu_write() argument
114 writel(reg_val, ccu->base + reg_offset); in __ccu_write()
312 u32 reg_val; in policy_init() local
314 reg_val = __ccu_read(ccu, offset); in policy_init()
315 reg_val |= mask; in policy_init()
316 __ccu_write(ccu, offset, reg_val); in policy_init()
[all …]

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