Home
last modified time | relevance | path

Searched refs:reg_tbl (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/media/platform/qcom/venus/
H A Dcore.c679 .reg_tbl = msm8916_reg_preset,
714 .reg_tbl = msm8939_reg_preset,
752 .reg_tbl = msm8996_reg_preset,
790 .reg_tbl = msm8998_reg_preset,
844 .reg_tbl = sdm660_reg_preset,
1027 .reg_tbl = sm8250_reg_preset,
1090 .reg_tbl = sm7280_reg_preset,
H A Dhfi_venus.c370 const struct reg_val *tbl = res->reg_tbl; in venus_set_registers()
/linux/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hw.h39 readl(((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
43 writel(value, ((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
H A Dqlcnic_83xx_hw.c263 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl; in qlcnic_83xx_register_map()
3616 sizeof(*adapter->ahw->reg_tbl)); in qlcnic_83xx_get_regs_len()
H A Dqlcnic_sriov_common.c665 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl; in qlcnic_sriov_vf_register_map()
H A Dqlcnic_main.c2450 ahw->reg_tbl = (u32 *) qlcnic_reg_tbl; in qlcnic_probe()
/linux/drivers/scsi/qla4xxx/
H A Dql4_def.h817 uint32_t *reg_tbl; member
1057 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]); in qla4_8xxx_rd_direct()
1064 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value); in qla4_8xxx_wr_direct()
H A Dql4_83xx.c453 ha->reg_tbl[QLA8XXX_CRB_DEV_PART_INFO]); in qla4_83xx_can_perform_reset()
455 drv_active = qla4_83xx_rd_reg(ha, ha->reg_tbl[QLA8XXX_CRB_DRV_ACTIVE]); in qla4_83xx_can_perform_reset()
/linux/drivers/net/ethernet/broadcom/
H A Dbnx2.c5573 } reg_tbl[] = { in bnx2_test_registers()
5687 for (i = 0; reg_tbl[i].offset != 0xffff; i++) { in bnx2_test_registers()
5689 u16 flags = reg_tbl[i].flags; in bnx2_test_registers()
5694 offset = (u32) reg_tbl[i].offset; in bnx2_test_registers()
5695 rw_mask = reg_tbl[i].rw_mask; in bnx2_test_registers()
5696 ro_mask = reg_tbl[i].ro_mask; in bnx2_test_registers()
5557 } reg_tbl[] = { bnx2_test_registers() local
H A Dtg3.c13175 } reg_tbl[] = { in tg3_test_registers() local
13318 for (i = 0; reg_tbl[i].offset != 0xffff; i++) { in tg3_test_registers()
13319 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) in tg3_test_registers()
13322 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) in tg3_test_registers()
13326 (reg_tbl[i].flags & TG3_FL_NOT_5788)) in tg3_test_registers()
13329 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) in tg3_test_registers()
13332 offset = (u32) reg_tbl[i].offset; in tg3_test_registers()
13333 read_mask = reg_tbl[i].read_mask; in tg3_test_registers()
13334 write_mask = reg_tbl[i].write_mask; in tg3_test_registers()