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Searched refs:reg_ofs (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/staging/vt6656/
H A Dmac.c80 int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits) in vnt_mac_reg_bits_off() argument
87 return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, reg_ofs, in vnt_mac_reg_bits_off()
91 int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits) in vnt_mac_reg_bits_on() argument
98 return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, reg_ofs, in vnt_mac_reg_bits_on()
102 int vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word) in vnt_mac_write_word() argument
109 return vnt_control_out(priv, MESSAGE_TYPE_WRITE, reg_ofs, in vnt_mac_write_word()
H A Dmac.h362 int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits);
363 int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits);
364 int vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word);
/linux/drivers/reset/
H A Dreset-ma35d1.c29 u32 reg_ofs; member
135 data->base + ma35d1_reset_map[id].reg_ofs); in ma35d1_restart_handler()
149 reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs); in ma35d1_reset_update()
154 writel_relaxed(reg, data->base + ma35d1_reset_map[id].reg_ofs); in ma35d1_reset_update()
178 reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs); in ma35d1_reset_status()
/linux/arch/arm/mach-bcm/
H A Dplatsmp-brcmstb.c132 const int reg_ofs = cpu_logical_map(cpu) * 8; in cpu_set_boot_addr() local
133 writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs); in cpu_set_boot_addr()
134 writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs); in cpu_set_boot_addr()
/linux/drivers/gpu/drm/imx/dcss/
H A Ddcss-ctxld.c333 u32 reg_ofs) in dcss_ctxld_write_irqsafe() argument
349 ctx[ctx_id][item_idx].ofs = reg_ofs; in dcss_ctxld_write_irqsafe()
354 u32 val, u32 reg_ofs) in dcss_ctxld_write() argument
357 dcss_ctxld_write_irqsafe(ctxld, ctx_id, val, reg_ofs); in dcss_ctxld_write()
H A Ddcss-dev.h116 u32 reg_ofs);
/linux/drivers/clk/
H A Dclk-cdce925.c212 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_prepare() local
218 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); in cdce925_pll_prepare()
247 reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]); in cdce925_pll_prepare()
250 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00); in cdce925_pll_prepare()
259 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_unprepare() local
262 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); in cdce925_pll_unprepare()
/linux/include/drm/bridge/
H A Dsamsung-dsim.h54 const unsigned int *reg_ofs; member
/linux/drivers/gpu/drm/bridge/
H A Dsamsung-dsim.c404 .reg_ofs = exynos_reg_ofs,
423 .reg_ofs = exynos_reg_ofs,
442 .reg_ofs = exynos_reg_ofs,
458 .reg_ofs = exynos5433_reg_ofs,
475 .reg_ofs = exynos5433_reg_ofs,
492 .reg_ofs = exynos5433_reg_ofs,
536 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in samsung_dsim_write()
541 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in samsung_dsim_read()