| /linux/drivers/i2c/busses/ |
| H A D | i2c-mv64xxx.c | 127 struct mv64xxx_i2c_regs reg_offsets; member
214 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset); in mv64xxx_i2c_hw_init()
216 drv_data->reg_base + drv_data->reg_offsets.clock); in mv64xxx_i2c_hw_init()
217 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr); in mv64xxx_i2c_hw_init()
218 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr); in mv64xxx_i2c_hw_init()
220 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_hw_init()
347 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_send_start()
375 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_do_action()
380 drv_data->reg_base + drv_data->reg_offsets.data); in mv64xxx_i2c_do_action()
382 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_do_action()
[all …]
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| /linux/arch/nios2/kernel/ |
| H A D | misaligned.c | 49 static int reg_offsets[32]; variable
53 u8 *p = ((u8 *)fp) + reg_offsets[reg]; in get_reg_val()
59 u8 *p = ((u8 *)fp) + reg_offsets[reg]; in put_reg_val()
214 reg_offsets[r] = offset; in misaligned_calc_reg_offsets()
222 reg_offsets[r] = offset; in misaligned_calc_reg_offsets()
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| /linux/drivers/pci/controller/dwc/ |
| H A D | pcie-al.c | 136 struct al_pcie_reg_offsets reg_offsets; member
188 pcie->reg_offsets.ob_ctrl = OB_CTRL_REV1_2_OFFSET; in al_pcie_reg_offsets_set()
192 pcie->reg_offsets.ob_ctrl = OB_CTRL_REV3_5_OFFSET; in al_pcie_reg_offsets_set()
213 pcie->reg_offsets.ob_ctrl + CFG_TARGET_BUS, in al_pcie_target_bus_set()
284 cfg_control_offset = AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl + in al_pcie_config_prepare()
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| /linux/arch/x86/um/ |
| H A D | ptrace_32.c | 31 static const int reg_offsets[] = { variable
96 child->thread.regs.regs.gp[reg_offsets[regno]] = value; in putreg()
148 return mask & child->thread.regs.regs.gp[reg_offsets[regno]]; in getreg()
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| H A D | ptrace_64.c | 24 static const int reg_offsets[] = variable
108 child->thread.regs.regs.gp[reg_offsets[regno >> 3]] = value; in putreg()
169 return mask & child->thread.regs.regs.gp[reg_offsets[regno >> 3]]; in getreg()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce112/ |
| H A D | dce112_hwseq.c | 42 static const struct dce112_hw_seq_reg_offsets reg_offsets[] = { variable
63 (reg + reg_offsets[id].crtc)
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| /linux/drivers/net/ethernet/8390/ |
| H A D | xsurf100.c | 254 static u32 reg_offsets[32]; in xsurf100_probe() local
277 reg_offsets[reg] = 4 * reg; in xsurf100_probe()
284 ax88796_data.ax.reg_offsets = reg_offsets; in xsurf100_probe()
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| /linux/drivers/cpufreq/ |
| H A D | mediatek-cpufreq-hw.c | 57 const u16 reg_offsets[REG_ARRAY_SIZE]; member
62 .reg_offsets = {
84 .reg_offsets = {
276 data->reg_bases[i] = base + priv->variant->reg_offsets[i]; in mtk_cpu_resources_init()
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| /linux/drivers/pci/controller/ |
| H A D | pcie-iproc-msi.c | 95 const u16 (*reg_offsets)[IPROC_MSI_REG_SIZE]; member
133 return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_read_reg()
142 writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_write_reg()
570 msi->reg_offsets = iproc_msi_reg_paxb; in iproc_msi_init()
575 msi->reg_offsets = iproc_msi_reg_paxc; in iproc_msi_init()
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| H A D | pcie-iproc.h | 89 u16 *reg_offsets; member
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| /linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| H A D | dce60_timing_generator.c | 51 static const struct dce110_timing_generator_offsets reg_offsets[] = { variable
254 tg110->derived_offsets = reg_offsets[instance]; in dce60_timing_generator_construct()
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| /linux/include/net/ |
| H A D | ax88796.h | 28 u32 *reg_offsets; /* register offsets */ member
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| H A D | dce110_compressor.c | 44 static const struct dce110_compressor_reg_offsets reg_offsets[] = { variable
78 cp110->offsets = reg_offsets[crtc_inst]; in reset_lb_on_vblank()
304 cp110->offsets = reg_offsets[params->inst]; in dce110_compressor_program_compressed_surface_address_and_pitch()
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| /linux/drivers/mtd/nand/raw/brcmnand/ |
| H A D | brcmnand.c | 297 const u16 *reg_offsets; member
712 ctrl->reg_offsets = brcmnand_regs_v72; in brcmnand_revision_init()
714 ctrl->reg_offsets = brcmnand_regs_v71; in brcmnand_revision_init()
716 ctrl->reg_offsets = brcmnand_regs_v60; in brcmnand_revision_init()
718 ctrl->reg_offsets = brcmnand_regs_v50; in brcmnand_revision_init()
720 ctrl->reg_offsets = brcmnand_regs_v33; in brcmnand_revision_init()
722 ctrl->reg_offsets = brcmnand_regs_v21; in brcmnand_revision_init()
830 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_read_reg()
841 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_write_reg()
955 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; in brcmnand_cs_offset()
[all …]
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| /linux/drivers/net/dsa/ |
| H A D | bcm_sf2.c | 1265 const u16 *reg_offsets; member
1295 .reg_offsets = bcm_sf2_4908_reg_offsets,
1321 .reg_offsets = bcm_sf2_7445_reg_offsets,
1344 .reg_offsets = bcm_sf2_7278_reg_offsets,
1406 priv->reg_offsets = data->reg_offsets; in bcm_sf2_sw_probe()
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| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_lrc.c | 619 static const u8 *reg_offsets(struct xe_device *xe, enum xe_engine_class class) in reg_offsets() function
987 set_offsets(regs, reg_offsets(gt_to_xe(gt), hwe->class), hwe); in empty_lrc_data()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 104 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { variable
120 (reg + reg_offsets[id].blnd)
123 (reg + reg_offsets[id].crtc)
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