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Searched refs:reg_off (Results 1 – 25 of 49) sorted by relevance

12

/linux/drivers/clk/meson/
H A Ds4-pll.c57 .reg_off = ANACTRL_FIXPLL_CTRL0,
62 .reg_off = ANACTRL_FIXPLL_CTRL0,
67 .reg_off = ANACTRL_FIXPLL_CTRL1,
72 .reg_off = ANACTRL_FIXPLL_CTRL0,
77 .reg_off = ANACTRL_FIXPLL_CTRL0,
82 .reg_off = ANACTRL_FIXPLL_CTRL0,
296 .reg_off = ANACTRL_GP0PLL_CTRL0,
301 .reg_off = ANACTRL_GP0PLL_CTRL0,
306 .reg_off = ANACTRL_GP0PLL_CTRL0,
311 .reg_off = ANACTRL_GP0PLL_CTRL0,
[all …]
H A Da1-pll.c32 .reg_off = ANACTRL_FIXPLL_CTRL0,
37 .reg_off = ANACTRL_FIXPLL_CTRL0,
42 .reg_off = ANACTRL_FIXPLL_CTRL0,
47 .reg_off = ANACTRL_FIXPLL_CTRL1,
52 .reg_off = ANACTRL_FIXPLL_STS,
57 .reg_off = ANACTRL_FIXPLL_CTRL0,
103 .reg_off = ANACTRL_HIFIPLL_CTRL0,
108 .reg_off = ANACTRL_HIFIPLL_CTRL0,
113 .reg_off = ANACTRL_HIFIPLL_CTRL0,
118 .reg_off = ANACTRL_HIFIPLL_CTRL1,
[all …]
H A Dc3-pll.c249 .reg_off = ANACTRL_GP0PLL_CTRL0,
254 .reg_off = ANACTRL_GP0PLL_CTRL0,
259 .reg_off = ANACTRL_GP0PLL_CTRL1,
264 .reg_off = ANACTRL_GP0PLL_CTRL0,
269 .reg_off = ANACTRL_GP0PLL_CTRL0,
274 .reg_off = ANACTRL_GP0PLL_CTRL0,
332 .reg_off = ANACTRL_HIFIPLL_CTRL0,
337 .reg_off = ANACTRL_HIFIPLL_CTRL0,
342 .reg_off = ANACTRL_HIFIPLL_CTRL1,
347 .reg_off = ANACTRL_HIFIPLL_CTRL0,
[all …]
H A Daxg.c114 .reg_off = HHI_MPLL_CNTL,
119 .reg_off = HHI_MPLL_CNTL,
124 .reg_off = HHI_MPLL_CNTL,
129 .reg_off = HHI_MPLL_CNTL2,
134 .reg_off = HHI_MPLL_CNTL,
139 .reg_off = HHI_MPLL_CNTL,
178 .reg_off = HHI_SYS_PLL_CNTL,
183 .reg_off = HHI_SYS_PLL_CNTL,
188 .reg_off = HHI_SYS_PLL_CNTL,
193 .reg_off = HHI_SYS_PLL_CNTL,
[all …]
H A Dmeson8-ddr.c29 .reg_off = AM_DDR_PLL_CNTL,
34 .reg_off = AM_DDR_PLL_CNTL,
39 .reg_off = AM_DDR_PLL_CNTL,
44 .reg_off = AM_DDR_PLL_CNTL,
49 .reg_off = AM_DDR_PLL_CNTL,
H A Dg12a-aoclk.c116 .reg_off = AO_RTC_ALT_CLK_CNTL0,
121 .reg_off = AO_RTC_ALT_CLK_CNTL0,
126 .reg_off = AO_RTC_ALT_CLK_CNTL1,
131 .reg_off = AO_RTC_ALT_CLK_CNTL1,
136 .reg_off = AO_RTC_ALT_CLK_CNTL0,
207 .reg_off = AO_CEC_CLK_CNTL_REG0,
212 .reg_off = AO_CEC_CLK_CNTL_REG0,
217 .reg_off = AO_CEC_CLK_CNTL_REG1,
222 .reg_off = AO_CEC_CLK_CNTL_REG1,
227 .reg_off = AO_CEC_CLK_CNTL_REG0,
H A Dgxbb.c122 .reg_off = HHI_MPLL_CNTL,
127 .reg_off = HHI_MPLL_CNTL,
132 .reg_off = HHI_MPLL_CNTL,
137 .reg_off = HHI_MPLL_CNTL2,
142 .reg_off = HHI_MPLL_CNTL,
147 .reg_off = HHI_MPLL_CNTL,
199 .reg_off = HHI_HDMI_PLL_CNTL,
204 .reg_off = HHI_HDMI_PLL_CNTL,
209 .reg_off = HHI_HDMI_PLL_CNTL,
214 .reg_off = HHI_HDMI_PLL_CNTL2,
[all …]
H A Dg12a.c143 .reg_off = HHI_FIX_PLL_CNTL0,
148 .reg_off = HHI_FIX_PLL_CNTL0,
153 .reg_off = HHI_FIX_PLL_CNTL0,
158 .reg_off = HHI_FIX_PLL_CNTL1,
163 .reg_off = HHI_FIX_PLL_CNTL0,
168 .reg_off = HHI_FIX_PLL_CNTL0,
212 .reg_off = HHI_SYS_PLL_CNTL0,
217 .reg_off = HHI_SYS_PLL_CNTL0,
222 .reg_off = HHI_SYS_PLL_CNTL0,
227 .reg_off = HHI_SYS_PLL_CNTL0,
[all …]
H A Dgxbb-aoclk.c80 .reg_off = AO_RTC_ALT_CLK_CNTL0,
85 .reg_off = AO_RTC_ALT_CLK_CNTL0,
90 .reg_off = AO_RTC_ALT_CLK_CNTL1,
95 .reg_off = AO_RTC_ALT_CLK_CNTL1,
100 .reg_off = AO_RTC_ALT_CLK_CNTL0,
H A Dparm.h25 u16 reg_off; member
34 regmap_read(map, p->reg_off, &val); in meson_parm_read()
41 regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift), in meson_parm_write()
H A Daxg-aoclk.c94 .reg_off = AO_RTC_ALT_CLK_CNTL0,
99 .reg_off = AO_RTC_ALT_CLK_CNTL0,
104 .reg_off = AO_RTC_ALT_CLK_CNTL1,
109 .reg_off = AO_RTC_ALT_CLK_CNTL1,
114 .reg_off = AO_RTC_ALT_CLK_CNTL0,
H A Dmeson8b.c125 .reg_off = HHI_MPLL_CNTL,
130 .reg_off = HHI_MPLL_CNTL,
135 .reg_off = HHI_MPLL_CNTL,
140 .reg_off = HHI_MPLL_CNTL2,
145 .reg_off = HHI_MPLL_CNTL,
150 .reg_off = HHI_MPLL_CNTL,
241 .reg_off = HHI_VID_PLL_CNTL,
246 .reg_off = HHI_VID_PLL_CNTL,
251 .reg_off = HHI_VID_PLL_CNTL,
256 .reg_off = HHI_VID_PLL_CNTL2,
[all …]
H A Da1-peripherals.c183 .reg_off = RTC_BY_OSCIN_CTRL0,
188 .reg_off = RTC_BY_OSCIN_CTRL0,
193 .reg_off = RTC_BY_OSCIN_CTRL1,
198 .reg_off = RTC_BY_OSCIN_CTRL1,
203 .reg_off = RTC_BY_OSCIN_CTRL0,
1647 .reg_off = CECA_CLK_CTRL0,
1652 .reg_off = CECA_CLK_CTRL0,
1657 .reg_off = CECA_CLK_CTRL1,
1662 .reg_off = CECA_CLK_CTRL1,
1667 .reg_off = CECA_CLK_CTRL0,
[all …]
/linux/tools/testing/selftests/kvm/riscv/
H A Dget-reg-list.c253 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG); in config_id_to_str() local
257 switch (reg_off) { in config_id_to_str()
276 return strdup_printf("%lld /* UNKNOWN */", reg_off); in config_id_to_str()
282 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE); in core_id_to_str() local
286 switch (reg_off) { in core_id_to_str()
299 reg_off - KVM_REG_RISCV_CORE_REG(regs.t0)); in core_id_to_str()
302 reg_off - KVM_REG_RISCV_CORE_REG(regs.s0)); in core_id_to_str()
305 reg_off - KVM_REG_RISCV_CORE_REG(regs.a0)); in core_id_to_str()
308 reg_off - KVM_REG_RISCV_CORE_REG(regs.s2) + 2); in core_id_to_str()
311 reg_off - KVM_REG_RISCV_CORE_REG(regs.t3) + 3); in core_id_to_str()
[all …]
/linux/drivers/mmc/host/
H A Dcavium.h37 #define MIO_EMM_CFG(x) (0x00 + x->reg_off)
38 #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off)
39 #define MIO_EMM_DMA(x) (0x50 + x->reg_off)
40 #define MIO_EMM_CMD(x) (0x58 + x->reg_off)
41 #define MIO_EMM_RSP_STS(x) (0x60 + x->reg_off)
42 #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off)
43 #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off)
44 #define MIO_EMM_INT(x) (0x78 + x->reg_off)
45 #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off)
46 #define MIO_EMM_WDOG(x) (0x88 + x->reg_off)
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-digicolor.c130 int bit_off, reg_off; in dc_set_mux() local
133 dc_client_sel(group, &reg_off, &bit_off); in dc_set_mux()
135 reg = readb_relaxed(pmap->regs + reg_off); in dc_set_mux()
138 writeb_relaxed(reg, pmap->regs + reg_off); in dc_set_mux()
148 int bit_off, reg_off; in dc_pmx_request_gpio() local
151 dc_client_sel(offset, &reg_off, &bit_off); in dc_pmx_request_gpio()
153 reg = readb_relaxed(pmap->regs + reg_off); in dc_pmx_request_gpio()
171 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); in dc_gpio_direction_input() local
177 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_input()
179 writeb_relaxed(drive, pmap->regs + reg_off); in dc_gpio_direction_input()
[all …]
/linux/sound/soc/tegra/
H A Dtegra210_mbdrc.c787 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; in tegra210_mbdrc_hw_params() local
790 reg_off + TEGRA210_MBDRC_CFG_RAM_CTRL, in tegra210_mbdrc_hw_params()
791 reg_off + TEGRA210_MBDRC_CFG_RAM_DATA, in tegra210_mbdrc_hw_params()
849 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; in tegra210_mbdrc_component_init() local
852 reg_off + TEGRA210_MBDRC_IIR_CFG, in tegra210_mbdrc_component_init()
858 reg_off + TEGRA210_MBDRC_IN_ATTACK, in tegra210_mbdrc_component_init()
864 reg_off + TEGRA210_MBDRC_IN_RELEASE, in tegra210_mbdrc_component_init()
870 reg_off + TEGRA210_MBDRC_FAST_ATTACK, in tegra210_mbdrc_component_init()
889 reg_off + TEGRA210_MBDRC_IN_THRESHOLD, in tegra210_mbdrc_component_init()
906 reg_off in tegra210_mbdrc_component_init()
[all...]
/linux/drivers/pinctrl/realtek/
H A Dpinctrl-rtd.c290 u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off; in rtd_pconf_parse_conf() local
307 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
320 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
332 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
345 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
358 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
366 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
400 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
403 reg_off += 0x4; in rtd_pconf_parse_conf()
418 reg_off = sconfig_desc->reg_offset; in rtd_pconf_parse_conf()
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
H A Docteon_device.h733 #define octeon_write_csr(oct_dev, reg_off, value) \ argument
734 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off))
736 #define octeon_write_csr64(oct_dev, reg_off, val64) \ argument
737 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off))
739 #define octeon_read_csr(oct_dev, reg_off) \ argument
740 readl((oct_dev)->mmio[0].hw_addr + (reg_off))
742 #define octeon_read_csr64(oct_dev, reg_off) \ argument
743 readq((oct_dev)->mmio[0].hw_addr + (reg_off))
/linux/drivers/nvmem/
H A Dimx-ocotp-ele.c31 u32 reg_off; member
69 void __iomem *reg = priv->base + priv->data->reg_off; in imx_ocotp_reg_read()
175 .reg_off = 0x8000,
190 .reg_off = 0x8000,
209 .reg_off = 0x8000,
/linux/drivers/pinctrl/spear/
H A Dpinctrl-plgpio.c85 u32 reg_off = REG_OFFSET(0, reg, pin); in is_plgpio_set() local
88 regmap_read(regmap, reg_off, &val); in is_plgpio_set()
96 u32 reg_off = REG_OFFSET(0, reg, pin); in plgpio_reg_set() local
100 regmap_update_bits(regmap, reg_off, mask, mask); in plgpio_reg_set()
106 u32 reg_off = REG_OFFSET(0, reg, pin); in plgpio_reg_reset() local
110 regmap_update_bits(regmap, reg_off, mask, 0); in plgpio_reg_reset()
333 u32 reg_off; in plgpio_irq_set_type() local
350 reg_off = REG_OFFSET(0, plgpio->regs.eit, offset); in plgpio_irq_set_type()
351 regmap_read(plgpio->regmap, reg_off, &val); in plgpio_irq_set_type()
355 regmap_write(plgpio->regmap, reg_off, val | (1 << offset)); in plgpio_irq_set_type()
[all …]
/linux/drivers/accel/habanalabs/goya/
H A Dgoya.c1088 u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI); in goya_init_dma_qman() local
1101 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address)); in goya_init_dma_qman()
1102 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address)); in goya_init_dma_qman()
1104 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH)); in goya_init_dma_qman()
1105 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); in goya_init_dma_qman()
1106 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); in goya_init_dma_qman()
1108 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); in goya_init_dma_qman()
1109 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); in goya_init_dma_qman()
1110 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); in goya_init_dma_qman()
1111 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); in goya_init_dma_qman()
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_util.c91 u32 reg_off, in dpu_reg_write() argument
98 name, reg_off, val); in dpu_reg_write()
99 writel_relaxed(val, c->blk_addr + reg_off); in dpu_reg_write()
102 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off) in dpu_reg_read() argument
104 return readl_relaxed(c->blk_addr + reg_off); in dpu_reg_read()
547 reg_val = DPU_REG_READ(c, clk_ctrl_reg->reg_off); in dpu_hw_clk_force_ctrl()
554 DPU_REG_WRITE(c, clk_ctrl_reg->reg_off, new_val); in dpu_hw_clk_force_ctrl()
/linux/sound/soc/mediatek/mt8365/
H A Dmt8365-dai-i2s.c287 unsigned int val, reg_off; in mt8365_dai_set_config() local
297 reg_off = i2s_data->reg_off_in; in mt8365_dai_set_config()
301 reg_off = i2s_data->reg_off_out; in mt8365_dai_set_config()
321 regmap_update_bits(afe->regmap, reg_off, ~(u32)AFE_I2S_CON_EN, val); in mt8365_dai_set_config()
501 unsigned int reg_off; in mt8365_dai_set_enable() local
504 reg_off = i2s_data->reg_off_in; in mt8365_dai_set_enable()
510 reg_off = i2s_data->reg_off_out; in mt8365_dai_set_enable()
512 regmap_update_bits(afe->regmap, reg_off, in mt8365_dai_set_enable()
/linux/sound/soc/xilinx/
H A Dxlnx_i2s.c94 u32 reg_off, chan_id; in xlnx_i2s_hw_params() local
120 reg_off = I2S_CH0_OFFSET + ((chan_id - 1) * 4); in xlnx_i2s_hw_params()
121 writel(chan_id, drv_data->base + reg_off); in xlnx_i2s_hw_params()

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