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Searched refs:reg_off (Results 1 – 25 of 57) sorted by relevance

123

/linux/tools/lib/bpf/
H A Dusdt.c219 short reg_off; member
1304 #define reg_off(reg64, reg32) offsetof(struct pt_regs, reg64) in calc_pt_regs_off() macro
1306 #define reg_off(reg64, reg32) offsetof(struct pt_regs, reg32) in calc_pt_regs_off()
1308 { {"rip", "eip", "", ""}, reg_off(rip, eip) }, in calc_pt_regs_off()
1309 { {"rax", "eax", "ax", "al"}, reg_off(rax, eax) }, in calc_pt_regs_off()
1310 { {"rbx", "ebx", "bx", "bl"}, reg_off(rbx, ebx) }, in calc_pt_regs_off()
1311 { {"rcx", "ecx", "cx", "cl"}, reg_off(rcx, ecx) }, in calc_pt_regs_off()
1312 { {"rdx", "edx", "dx", "dl"}, reg_off(rdx, edx) }, in calc_pt_regs_off()
1313 { {"rsi", "esi", "si", "sil"}, reg_off(rsi, esi) }, in calc_pt_regs_off()
1314 { {"rdi", "edi", "di", "dil"}, reg_off(rdi, edi) }, in calc_pt_regs_off()
[all …]
/linux/drivers/mmc/host/
H A Dcavium.h37 #define MIO_EMM_CFG(x) (0x00 + x->reg_off)
38 #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off)
39 #define MIO_EMM_DMA(x) (0x50 + x->reg_off)
40 #define MIO_EMM_CMD(x) (0x58 + x->reg_off)
41 #define MIO_EMM_RSP_STS(x) (0x60 + x->reg_off)
42 #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off)
43 #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off)
44 #define MIO_EMM_INT(x) (0x78 + x->reg_off)
45 #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off)
46 #define MIO_EMM_WDOG(x) (0x88 + x->reg_off)
[all …]
/linux/drivers/clk/meson/
H A Ds4-pll.c57 .reg_off = ANACTRL_FIXPLL_CTRL0,
62 .reg_off = ANACTRL_FIXPLL_CTRL0,
67 .reg_off = ANACTRL_FIXPLL_CTRL1,
72 .reg_off = ANACTRL_FIXPLL_CTRL0,
77 .reg_off = ANACTRL_FIXPLL_CTRL0,
82 .reg_off = ANACTRL_FIXPLL_CTRL0,
296 .reg_off = ANACTRL_GP0PLL_CTRL0,
301 .reg_off = ANACTRL_GP0PLL_CTRL0,
306 .reg_off = ANACTRL_GP0PLL_CTRL0,
311 .reg_off = ANACTRL_GP0PLL_CTRL0,
[all …]
H A Da1-pll.c31 .reg_off = ANACTRL_FIXPLL_CTRL0,
36 .reg_off = ANACTRL_FIXPLL_CTRL0,
41 .reg_off = ANACTRL_FIXPLL_CTRL0,
46 .reg_off = ANACTRL_FIXPLL_CTRL1,
51 .reg_off = ANACTRL_FIXPLL_STS,
56 .reg_off = ANACTRL_FIXPLL_CTRL0,
102 .reg_off = ANACTRL_HIFIPLL_CTRL0,
107 .reg_off = ANACTRL_HIFIPLL_CTRL0,
112 .reg_off = ANACTRL_HIFIPLL_CTRL0,
117 .reg_off = ANACTRL_HIFIPLL_CTRL1,
[all …]
H A Dc3-pll.c249 .reg_off = ANACTRL_GP0PLL_CTRL0,
254 .reg_off = ANACTRL_GP0PLL_CTRL0,
259 .reg_off = ANACTRL_GP0PLL_CTRL1,
264 .reg_off = ANACTRL_GP0PLL_CTRL0,
269 .reg_off = ANACTRL_GP0PLL_CTRL0,
274 .reg_off = ANACTRL_GP0PLL_CTRL0,
332 .reg_off = ANACTRL_HIFIPLL_CTRL0,
337 .reg_off = ANACTRL_HIFIPLL_CTRL0,
342 .reg_off = ANACTRL_HIFIPLL_CTRL1,
347 .reg_off = ANACTRL_HIFIPLL_CTRL0,
[all …]
H A Dmeson8-ddr.c29 .reg_off = AM_DDR_PLL_CNTL,
34 .reg_off = AM_DDR_PLL_CNTL,
39 .reg_off = AM_DDR_PLL_CNTL,
44 .reg_off = AM_DDR_PLL_CNTL,
49 .reg_off = AM_DDR_PLL_CNTL,
H A Daxg.c113 .reg_off = HHI_MPLL_CNTL,
118 .reg_off = HHI_MPLL_CNTL,
123 .reg_off = HHI_MPLL_CNTL,
128 .reg_off = HHI_MPLL_CNTL2,
133 .reg_off = HHI_MPLL_CNTL,
138 .reg_off = HHI_MPLL_CNTL,
177 .reg_off = HHI_SYS_PLL_CNTL,
182 .reg_off = HHI_SYS_PLL_CNTL,
187 .reg_off = HHI_SYS_PLL_CNTL,
192 .reg_off = HHI_SYS_PLL_CNTL,
[all …]
H A Dg12a-aoclk.c116 .reg_off = AO_RTC_ALT_CLK_CNTL0,
121 .reg_off = AO_RTC_ALT_CLK_CNTL0,
126 .reg_off = AO_RTC_ALT_CLK_CNTL1,
131 .reg_off = AO_RTC_ALT_CLK_CNTL1,
136 .reg_off = AO_RTC_ALT_CLK_CNTL0,
207 .reg_off = AO_CEC_CLK_CNTL_REG0,
212 .reg_off = AO_CEC_CLK_CNTL_REG0,
217 .reg_off = AO_CEC_CLK_CNTL_REG1,
222 .reg_off = AO_CEC_CLK_CNTL_REG1,
227 .reg_off = AO_CEC_CLK_CNTL_REG0,
H A Da9-aoclk.c198 .reg_off = AO_RTC_BY_OSCIN_CTRL0,
203 .reg_off = AO_RTC_BY_OSCIN_CTRL0,
208 .reg_off = AO_RTC_BY_OSCIN_CTRL1,
213 .reg_off = AO_RTC_BY_OSCIN_CTRL1,
218 .reg_off = AO_RTC_BY_OSCIN_CTRL0,
304 .reg_off = AO_CEC_CTRL0,
309 .reg_off = AO_CEC_CTRL0,
314 .reg_off = AO_CEC_CTRL1,
319 .reg_off = AO_CEC_CTRL1,
324 .reg_off = AO_CEC_CTRL0,
H A Dgxbb.c121 .reg_off = HHI_MPLL_CNTL,
126 .reg_off = HHI_MPLL_CNTL,
131 .reg_off = HHI_MPLL_CNTL,
136 .reg_off = HHI_MPLL_CNTL2,
141 .reg_off = HHI_MPLL_CNTL,
146 .reg_off = HHI_MPLL_CNTL,
198 .reg_off = HHI_HDMI_PLL_CNTL,
203 .reg_off = HHI_HDMI_PLL_CNTL,
208 .reg_off = HHI_HDMI_PLL_CNTL,
213 .reg_off = HHI_HDMI_PLL_CNTL2,
[all …]
H A Dparm.h25 u16 reg_off; member
34 regmap_read(map, p->reg_off, &val); in meson_parm_read()
41 regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift), in meson_parm_write()
H A Dgxbb-aoclk.c80 .reg_off = AO_RTC_ALT_CLK_CNTL0,
85 .reg_off = AO_RTC_ALT_CLK_CNTL0,
90 .reg_off = AO_RTC_ALT_CLK_CNTL1,
95 .reg_off = AO_RTC_ALT_CLK_CNTL1,
100 .reg_off = AO_RTC_ALT_CLK_CNTL0,
H A Daxg-aoclk.c94 .reg_off = AO_RTC_ALT_CLK_CNTL0,
99 .reg_off = AO_RTC_ALT_CLK_CNTL0,
104 .reg_off = AO_RTC_ALT_CLK_CNTL1,
109 .reg_off = AO_RTC_ALT_CLK_CNTL1,
114 .reg_off = AO_RTC_ALT_CLK_CNTL0,
/linux/drivers/pinctrl/sunplus/
H A Dsppctl.c112 static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off) in sppctl_get_reg_and_bit_offset() argument
117 *reg_off = (offset / 32) * 4; in sppctl_get_reg_and_bit_offset()
123 static inline u32 sppctl_get_moon_reg_and_bit_offset(unsigned int offset, u32 *reg_off) in sppctl_get_moon_reg_and_bit_offset() argument
133 *reg_off = (offset / 16) * 4; in sppctl_get_moon_reg_and_bit_offset()
139 static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_off, int val) in sppctl_prep_moon_reg_and_offset() argument
143 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off); in sppctl_prep_moon_reg_and_offset()
227 static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 bit_sz, in sppctl_gmx_set() argument
240 writel(reg, pctl->moon1_base + reg_off * 4); in sppctl_gmx_set()
264 u32 reg_off, bit_off, reg; in sppctl_first_get() local
266 bit_off = sppctl_get_reg_and_bit_offset(offset, &reg_off); in sppctl_first_get()
[all …]
/linux/tools/testing/selftests/kvm/riscv/
H A Dget-reg-list.c290 /* reg_off is the offset into struct kvm_riscv_config */ in core_id_to_str()
291 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG); in core_id_to_str()
295 switch (reg_off) { in core_id_to_str()
314 return strdup_printf("%lld /* UNKNOWN */", reg_off); in core_id_to_str()
319 /* reg_off is the offset into struct kvm_riscv_core */ in core_id_to_str()
320 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE); in core_id_to_str()
324 switch (reg_off) {
337 reg_off - KVM_REG_RISCV_CORE_REG(regs.t0)); in general_csr_id_to_str()
340 reg_off - KVM_REG_RISCV_CORE_REG(regs.s0)); in general_csr_id_to_str()
343 reg_off in general_csr_id_to_str()
256 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG); config_id_to_str() local
285 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE); core_id_to_str() local
329 general_csr_id_to_str(__u64 reg_off) general_csr_id_to_str() argument
360 aia_csr_id_to_str(__u64 reg_off) aia_csr_id_to_str() argument
383 smstateen_csr_id_to_str(__u64 reg_off) smstateen_csr_id_to_str() argument
397 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR); csr_id_to_str() local
419 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_TIMER); timer_id_to_str() local
440 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_F); fp_f_id_to_str() local
458 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_D); fp_d_id_to_str() local
476 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_VECTOR); vector_id_to_str() local
505 isa_ext_single_id_to_str(__u64 reg_off) isa_ext_single_id_to_str() argument
594 isa_ext_multi_id_to_str(__u64 reg_subtype,__u64 reg_off) isa_ext_multi_id_to_str() argument
613 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT); isa_ext_id_to_str() local
634 sbi_ext_single_id_to_str(__u64 reg_off) sbi_ext_single_id_to_str() argument
660 sbi_ext_multi_id_to_str(__u64 reg_subtype,__u64 reg_off) sbi_ext_multi_id_to_str() argument
679 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_EXT); sbi_ext_id_to_str() local
697 sbi_sta_id_to_str(__u64 reg_off) sbi_sta_id_to_str() argument
706 sbi_fwft_id_to_str(__u64 reg_off) sbi_fwft_id_to_str() argument
721 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_STATE); sbi_id_to_str() local
[all...]
/linux/drivers/pinctrl/
H A Dpinctrl-digicolor.c129 int bit_off, reg_off; in dc_set_mux() local
132 dc_client_sel(group, &reg_off, &bit_off); in dc_set_mux()
134 reg = readb_relaxed(pmap->regs + reg_off); in dc_set_mux()
137 writeb_relaxed(reg, pmap->regs + reg_off); in dc_set_mux()
147 int bit_off, reg_off; in dc_pmx_request_gpio() local
150 dc_client_sel(offset, &reg_off, &bit_off); in dc_pmx_request_gpio()
152 reg = readb_relaxed(pmap->regs + reg_off); in dc_pmx_request_gpio()
170 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); in dc_gpio_direction_input() local
176 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_input()
178 writeb_relaxed(drive, pmap->regs + reg_off); in dc_gpio_direction_input()
[all …]
/linux/sound/soc/tegra/
H A Dtegra210_mbdrc.c794 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; in tegra210_mbdrc_hw_params()
797 reg_off + TEGRA210_MBDRC_CFG_RAM_CTRL,
798 reg_off + TEGRA210_MBDRC_CFG_RAM_DATA, in tegra210_mbdrc_component_init()
856 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; in tegra210_mbdrc_component_init()
859 reg_off + TEGRA210_MBDRC_IIR_CFG, in tegra210_mbdrc_component_init()
865 reg_off + TEGRA210_MBDRC_IN_ATTACK, in tegra210_mbdrc_component_init()
871 reg_off + TEGRA210_MBDRC_IN_RELEASE, in tegra210_mbdrc_component_init()
877 reg_off + TEGRA210_MBDRC_FAST_ATTACK, in tegra210_mbdrc_component_init()
896 reg_off + TEGRA210_MBDRC_IN_THRESHOLD, in tegra210_mbdrc_component_init()
913 reg_off in tegra210_mbdrc_component_init()
787 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; tegra210_mbdrc_hw_params() local
849 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; tegra210_mbdrc_component_init() local
[all...]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_8_1_sm8450.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_8_4_sa8775p.h24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
32 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_8_0_sc8280xp.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
/linux/drivers/net/ethernet/cavium/liquidio/
H A Docteon_device.h730 #define octeon_write_csr(oct_dev, reg_off, value) \ argument
731 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off))
733 #define octeon_write_csr64(oct_dev, reg_off, val64) \ argument
734 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off))
736 #define octeon_read_csr(oct_dev, reg_off) \ argument
737 readl((oct_dev)->mmio[0].hw_addr + (reg_off))
739 #define octeon_read_csr64(oct_dev, reg_off) \ argument
740 readq((oct_dev)->mmio[0].hw_addr + (reg_off))
/linux/drivers/nvmem/
H A Dimx-ocotp-ele.c31 u32 reg_off; member
69 void __iomem *reg = priv->base + priv->data->reg_off; in imx_ocotp_reg_read()
176 .reg_off = 0x8000,
191 .reg_off = 0x8000,
210 .reg_off = 0x8000,
/linux/drivers/pinctrl/spear/
H A Dpinctrl-plgpio.c85 u32 reg_off = REG_OFFSET(0, reg, pin); in is_plgpio_set() local
88 regmap_read(regmap, reg_off, &val); in is_plgpio_set()
96 u32 reg_off = REG_OFFSET(0, reg, pin); in plgpio_reg_set() local
100 regmap_update_bits(regmap, reg_off, mask, mask); in plgpio_reg_set()
106 u32 reg_off = REG_OFFSET(0, reg, pin); in plgpio_reg_reset() local
110 regmap_update_bits(regmap, reg_off, mask, 0); in plgpio_reg_reset()
333 u32 reg_off; in plgpio_irq_set_type() local
350 reg_off = REG_OFFSET(0, plgpio->regs.eit, offset); in plgpio_irq_set_type()
351 regmap_read(plgpio->regmap, reg_off, &val); in plgpio_irq_set_type()
355 regmap_write(plgpio->regmap, reg_off, val | (1 << offset)); in plgpio_irq_set_type()
[all …]
/linux/drivers/mtd/nand/
H A Dqpic_common.c231 int reg_off, const void *vaddr, in qcom_prep_bam_dma_desc_cmd() argument
249 offset = nandc->props->bam_offset + reg_off + 4 * i; in qcom_prep_bam_dma_desc_cmd()
356 int reg_off, const void *vaddr, int size, in qcom_prep_adm_dma_desc() argument
392 slave_conf.src_addr = nandc->base_dma + reg_off; in qcom_prep_adm_dma_desc()
400 slave_conf.dst_addr = nandc->base_dma + reg_off; in qcom_prep_adm_dma_desc()
516 int qcom_read_data_dma(struct qcom_nand_controller *nandc, int reg_off, in qcom_read_data_dma() argument
522 return qcom_prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); in qcom_read_data_dma()
537 int qcom_write_data_dma(struct qcom_nand_controller *nandc, int reg_off, in qcom_write_data_dma() argument
543 return qcom_prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); in qcom_write_data_dma()
/linux/drivers/accel/habanalabs/goya/
H A Dgoya.c1087 u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI); in goya_init_dma_qman() local
1100 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address)); in goya_init_dma_qman()
1101 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address)); in goya_init_dma_qman()
1103 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH)); in goya_init_dma_qman()
1104 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); in goya_init_dma_qman()
1105 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); in goya_init_dma_qman()
1107 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); in goya_init_dma_qman()
1108 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); in goya_init_dma_qman()
1109 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); in goya_init_dma_qman()
1110 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); in goya_init_dma_qman()
[all …]

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