| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
| H A D | irq_service_dcn303.c | 121 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
122 .enable_reg = SRI(reg1, block, reg_num),\
123 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
125 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
126 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
128 .ack_reg = SRI(reg2, block, reg_num),\
129 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
130 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
134 #define hpd_int_entry(reg_num)\ argument
135 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/ |
| H A D | irq_service_dcn201.c | 125 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
126 .enable_reg = SRI(reg1, block, reg_num),\
128 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
130 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
131 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
133 .ack_reg = SRI(reg2, block, reg_num),\
135 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
137 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
139 #define hpd_int_entry(reg_num)\ argument
140 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dce120/ |
| H A D | irq_service_dce120.c | 76 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
77 .enable_reg = SRI(reg1, block, reg_num),\
79 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
81 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
82 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
84 .ack_reg = SRI(reg2, block, reg_num),\
86 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
88 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
90 #define hpd_int_entry(reg_num)\ argument
91 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn36/ |
| H A D | irq_service_dcn36.c | 158 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
159 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
160 REG_STRUCT[base + reg_num].enable_mask = \
161 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
162 REG_STRUCT[base + reg_num].enable_value[0] = \
163 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
164 REG_STRUCT[base + reg_num].enable_value[1] = \
165 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
166 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
167 REG_STRUCT[base + reg_num].ack_mask = \
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn35/ |
| H A D | irq_service_dcn35.c | 180 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
181 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
182 REG_STRUCT[base + reg_num].enable_mask = \
183 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
184 REG_STRUCT[base + reg_num].enable_value[0] = \
185 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
186 REG_STRUCT[base + reg_num].enable_value[1] = \
187 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
188 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
189 REG_STRUCT[base + reg_num].ack_mask = \
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn351/ |
| H A D | irq_service_dcn351.c | 159 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
160 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
161 REG_STRUCT[base + reg_num].enable_mask = \
162 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
163 REG_STRUCT[base + reg_num].enable_value[0] = \
164 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
165 REG_STRUCT[base + reg_num].enable_value[1] = \
166 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
167 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
168 REG_STRUCT[base + reg_num].ack_mask = \
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dce80/ |
| H A D | irq_service_dce80.c | 65 #define hpd_int_entry(reg_num)\ argument
66 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
67 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
73 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
76 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
80 #define hpd_rx_int_entry(reg_num)\ argument
81 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
82 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
87 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
90 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn32/ |
| H A D | irq_service_dcn32.c | 192 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
193 .enable_reg = SRI(reg1, block, reg_num),\
195 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
197 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
198 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
200 .ack_reg = SRI(reg2, block, reg_num),\
202 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
220 #define hpd_int_entry(reg_num)\ argument
221 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn401/ |
| H A D | irq_service_dcn401.c | 172 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
173 .enable_reg = SRI(reg1, block, reg_num),\
175 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
177 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
178 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
180 .ack_reg = SRI(reg2, block, reg_num),\
182 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
184 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
200 #define hpd_int_entry(reg_num)\ argument
201 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
| H A D | irq_service_dcn20.c | 176 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
177 .enable_reg = SRI(reg1, block, reg_num),\
179 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
181 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
182 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
184 .ack_reg = SRI(reg2, block, reg_num),\
186 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
188 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
192 #define hpd_int_entry(reg_num)\ argument
193 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
| H A D | irq_service_dcn10.c | 173 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
174 .enable_reg = SRI(reg1, block, reg_num),\
176 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
178 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
179 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
181 .ack_reg = SRI(reg2, block, reg_num),\
183 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
185 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
187 #define hpd_int_entry(reg_num)\ argument
188 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
| H A D | irq_service_dcn302.c | 178 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
179 .enable_reg = SRI(reg1, block, reg_num),\
180 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
182 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
183 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
185 .ack_reg = SRI(reg2, block, reg_num),\
186 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
187 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
210 #define hpd_int_entry(reg_num)\ argument
211 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dce60/ |
| H A D | irq_service_dce60.c | 74 #define hpd_int_entry(reg_num)\ argument
75 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
76 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
82 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
85 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
89 #define hpd_rx_int_entry(reg_num)\ argument
90 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
91 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
96 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
99 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
| H A D | irq_service_dcn21.c | 186 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
187 .enable_reg = SRI(reg1, block, reg_num),\
189 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
192 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
194 .ack_reg = SRI(reg2, block, reg_num),\
196 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
198 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
214 #define hpd_int_entry(reg_num)\ argument
215 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
| H A D | irq_service_dcn30.c | 193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
194 .enable_reg = SRI(reg1, block, reg_num),\
196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
198 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
201 .ack_reg = SRI(reg2, block, reg_num),\
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
205 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
221 #define hpd_int_entry(reg_num)\ argument
222 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/ |
| H A D | irq_service_dcn315.c | 188 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
189 .enable_reg = SRI(reg1, block, reg_num),\
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
193 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
194 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
196 .ack_reg = SRI(reg2, block, reg_num),\
198 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
200 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
216 #define hpd_int_entry(reg_num)\ argument
217 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
| H A D | irq_service_dcn31.c | 181 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
182 .enable_reg = SRI(reg1, block, reg_num),\
184 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
186 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
187 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
189 .ack_reg = SRI(reg2, block, reg_num),\
191 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
193 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
209 #define hpd_int_entry(reg_num)\ argument
210 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn314/ |
| H A D | irq_service_dcn314.c | 183 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
184 .enable_reg = SRI(reg1, block, reg_num),\
186 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
188 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
189 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
191 .ack_reg = SRI(reg2, block, reg_num),\
193 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
195 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
211 #define hpd_int_entry(reg_num)\ argument
212 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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| /linux/arch/sparc/kernel/ |
| H A D | pcr.c | 55 static u64 direct_pcr_read(unsigned long reg_num) in direct_pcr_read() argument
59 WARN_ON_ONCE(reg_num != 0); in direct_pcr_read()
64 static void direct_pcr_write(unsigned long reg_num, u64 val) in direct_pcr_write() argument
66 WARN_ON_ONCE(reg_num != 0); in direct_pcr_write()
70 static u64 direct_pic_read(unsigned long reg_num) in direct_pic_read() argument
74 WARN_ON_ONCE(reg_num != 0); in direct_pic_read()
79 static void direct_pic_write(unsigned long reg_num, u64 val) in direct_pic_write() argument
81 WARN_ON_ONCE(reg_num != 0); in direct_pic_write()
111 static void n2_pcr_write(unsigned long reg_num, u64 val) in n2_pcr_write() argument
115 WARN_ON_ONCE(reg_num != 0); in n2_pcr_write()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dce110/ |
| H A D | irq_service_dce110.c | 89 #define hpd_int_entry(reg_num)\ argument
90 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
91 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
97 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
100 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
104 #define hpd_rx_int_entry(reg_num)\ argument
105 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
106 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
111 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
114 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
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| /linux/arch/riscv/kvm/ |
| H A D | vcpu_fp.c | 84 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_fp() local
93 if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr)) in kvm_riscv_vcpu_get_reg_fp()
95 else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <= reg_num) && in kvm_riscv_vcpu_get_reg_fp()
96 reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) in kvm_riscv_vcpu_get_reg_fp()
97 reg_val = &cntx->fp.f.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp()
102 if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { in kvm_riscv_vcpu_get_reg_fp()
106 } else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <= reg_num) && in kvm_riscv_vcpu_get_reg_fp()
107 reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) { in kvm_riscv_vcpu_get_reg_fp()
110 reg_val = &cntx->fp.d.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp()
129 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_fp() local
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| H A D | vcpu_sbi.c | 219 unsigned long reg_num, in riscv_vcpu_set_sbi_ext_single() argument
228 sext = riscv_vcpu_get_sbi_ext(vcpu, reg_num); in riscv_vcpu_set_sbi_ext_single()
240 unsigned long reg_num, in riscv_vcpu_get_sbi_ext_single() argument
246 sext = riscv_vcpu_get_sbi_ext(vcpu, reg_num); in riscv_vcpu_get_sbi_ext_single()
257 unsigned long reg_num, in riscv_vcpu_set_sbi_ext_multi() argument
262 if (reg_num > KVM_REG_RISCV_SBI_MULTI_REG_LAST) in riscv_vcpu_set_sbi_ext_multi()
266 ext_id = i + reg_num * BITS_PER_LONG; in riscv_vcpu_set_sbi_ext_multi()
277 unsigned long reg_num, in riscv_vcpu_get_sbi_ext_multi() argument
282 if (reg_num > KVM_REG_RISCV_SBI_MULTI_REG_LAST) in riscv_vcpu_get_sbi_ext_multi()
286 ext_id = i + reg_num * BITS_PER_LONG; in riscv_vcpu_get_sbi_ext_multi()
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| /linux/drivers/video/fbdev/via/ |
| H A D | hw.h | 355 int reg_num; member
361 int reg_num; member
367 int reg_num; member
373 int reg_num; member
379 int reg_num; member
385 int reg_num; member
391 int reg_num; member
397 int reg_num; member
403 int reg_num; member
409 int reg_num; member
[all …]
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| /linux/drivers/net/ethernet/hisilicon/hns3/hns3vf/ |
| H A D | hclgevf_regs.c | 130 int i, j, reg_num; in hclgevf_get_regs() local
137 reg_num = ARRAY_SIZE(cmdq_reg_addr_list); in hclgevf_get_regs()
138 reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_CMDQ, reg_num, reg); in hclgevf_get_regs()
139 for (i = 0; i < reg_num; i++) in hclgevf_get_regs()
142 reg_num = ARRAY_SIZE(common_reg_addr_list); in hclgevf_get_regs()
143 reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_COMMON, reg_num, reg); in hclgevf_get_regs()
144 for (i = 0; i < reg_num; i++) in hclgevf_get_regs()
147 reg_num = ARRAY_SIZE(ring_reg_addr_list); in hclgevf_get_regs()
149 reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_RING, reg_num, reg); in hclgevf_get_regs()
151 for (i = 0; i < reg_num; i++) in hclgevf_get_regs()
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| /linux/drivers/irqchip/ |
| H A D | irq-imx-irqsteer.c | 35 int reg_num; member
45 return (data->reg_num - irqnum / 32 - 1); in imx_irqsteer_get_reg_index()
56 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask()
58 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask()
70 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_mask()
72 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_mask()
146 if (hwirq >= data->reg_num * 32) in imx_irqsteer_irq_handler()
150 CHANSTATUS(idx, data->reg_num)); in imx_irqsteer_irq_handler()
196 data->reg_num = irqs_num / 32; in imx_irqsteer_probe()
200 sizeof(u32) * data->reg_num, in imx_irqsteer_probe()
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