Home
last modified time | relevance | path

Searched refs:reg_name (Results 1 – 25 of 147) sorted by relevance

123456

/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h37 #define REG_OFFSET(reg_name) (BASE(mm##reg_name##_BASE_IDX) + mm##reg_name) argument
39 #define FD_SHIFT(reg_name, field) reg_name##__##field##__SHIFT argument
41 #define FD_MASK(reg_name, field) reg_name##__##field##_MASK argument
47 #define FN(reg_name, field) FD(reg_name##__##field) argument
58 #define REG_SET_N(reg_name, n, initial_val, ...) \ argument
59 dmub_reg_set(CTX, REG(reg_name), initial_val, n, __VA_ARGS__)
61 #define REG_SET(reg_name, initial_val, field, val) \ argument
62 REG_SET_N(reg_name, 1, initial_val, \
63 FN(reg_name, field), val)
85 #define REG_UPDATE_N(reg_name, n, ...)\ argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
H A Dhw_factory_dcn21.c57 #define REG(reg_name)\ argument
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
60 #define SF_HPD(reg_name, field_name, post_fix)\ argument
61 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
63 #define REGI(reg_name, block, id)\ argument
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
65 mm ## block ## id ## _ ## reg_name
67 #define SF(reg_name, field_name, post_fix)\ argument
68 .field_name = reg_name ## __ ## field_name ## post_fix
99 #define SF_DDC(reg_name, field_name, post_fix)\ argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/
H A Dhw_factory_dce120.c46 #define SF_HPD(reg_name, field_name, post_fix)\ argument
47 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
50 #define SF_HPD(reg_name, field_name, post_fix)\ argument
51 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
60 #define REG(reg_name)\ argument
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
63 #define REGI(reg_name, block, id)\ argument
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
65 mm ## block ## id ## _ ## reg_name
96 #define SF_DDC(reg_name, field_name, post_fix)\ argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
H A Dhw_factory_dcn32.c59 #define REG(reg_name)\ argument
60 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
63 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
65 #define REGI(reg_name, block, id)\ argument
66 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
67 reg ## block ## id ## _ ## reg_name
69 #define SF(reg_name, field_name, post_fix)\ argument
70 .field_name = reg_name ## __ ## field_name ## post_fix
101 #define SF_DDC(reg_name, field_name, post_fix)\ argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_factory_dcn30.c66 #define REG(reg_name)\ argument
67 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
69 #define SF_HPD(reg_name, field_name, post_fix)\ argument
70 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
72 #define REGI(reg_name, block, id)\ argument
73 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
74 mm ## block ## id ## _ ## reg_name
76 #define SF(reg_name, field_name, post_fix)\ argument
77 .field_name = reg_name ## __ ## field_name ## post_fix
109 #define SF_DDC(reg_name, field_name, post_fix)\ argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
H A Dhw_factory_dcn315.c63 #define REG(reg_name)\ argument
64 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
66 #define SF_HPD(reg_name, field_name, post_fix)\ argument
67 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
69 #define REGI(reg_name, block, id)\ argument
70 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
71 reg ## block ## id ## _ ## reg_name
73 #define SF(reg_name, field_name, post_fix)\ argument
74 .field_name = reg_name ## __ ## field_name ## post_fix
105 #define SF_DDC(reg_name, field_name, post_fix)\ argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
H A Dhw_factory_dcn20.c59 #define REG(reg_name)\ argument
60 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
63 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
65 #define REGI(reg_name, block, id)\ argument
66 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
67 mm ## block ## id ## _ ## reg_name
69 #define SF(reg_name, field_name, post_fix)\ argument
70 .field_name = reg_name ## __ ## field_name ## post_fix
102 #define SF_DDC(reg_name, field_name, post_fix)\ argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn401/
H A Dhw_factory_dcn401.c39 #define REG(reg_name)\ argument
40 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
43 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
45 #define REGI(reg_name, block, id)\ argument
46 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
47 reg ## block ## id ## _ ## reg_name
49 #define SF(reg_name, field_name, post_fix)\ argument
50 .field_name = reg_name ## __ ## field_name ## post_fix
81 #define SF_DDC(reg_name, field_name, post_fix)\ argument
[all …]
/linux/tools/perf/util/
H A Dperf_regs.c129 const char *reg_name = NULL; in perf_reg_name()
133 reg_name = __perf_reg_name_arm(id); in perf_reg_name()
136 reg_name = __perf_reg_name_arm64(id); in perf_reg_name()
139 reg_name = __perf_reg_name_csky(id, e_flags); in perf_reg_name()
142 reg_name = __perf_reg_name_loongarch(id); in perf_reg_name()
145 reg_name = __perf_reg_name_mips(id); in perf_reg_name()
149 reg_name = __perf_reg_name_powerpc(id); in perf_reg_name()
152 reg_name = __perf_reg_name_riscv(id); in perf_reg_name()
155 reg_name = __perf_reg_name_s390(id); in perf_reg_name()
159 reg_name in perf_reg_name()
123 const char *reg_name = NULL; perf_reg_name() local
[all...]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
H A Dhw_factory_dcn10.c47 #define SF_HPD(reg_name, field_name, post_fix)\ argument
48 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
57 #define REG(reg_name)\ argument
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
60 #define REGI(reg_name, block, id)\ argument
61 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
62 mm ## block ## id ## _ ## reg_name
92 #define SF_DDC(reg_name, field_name, post_fix)\ argument
93 .field_name = reg_name ## __ ## field_name ## post_fix
128 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn60/
H A Ddcn60_resource.c110 #define SR(reg_name)\ argument
111 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
112 reg ## reg_name
113 #define SR_ARR(reg_name, id)\ argument
114 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
115 reg ## reg_name
116 #define SR_ARR_INIT(reg_name, id, value)\ argument
117 REG_STRUCT[id].reg_name = value
119 #define SRI(reg_name, block, id)\ argument
120 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_panel_cntl.h32 #define DCE_PANEL_CNTL_SR(reg_name, block)\ argument
33 .reg_name = mm ## block ## _ ## reg_name
45 #define DCN_PANEL_CNTL_SR(reg_name, block)\ argument
46 .reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \
47 mm ## block ## _ ## reg_name
59 #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\ argument
60 .field_name = reg_name ## __ ## field_name ## post_fix
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c121 #define SR(reg_name)\ argument
122 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
123 reg ## reg_name
124 #define SR_ARR(reg_name, id)\ argument
125 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
126 reg ## reg_name
127 #define SR_ARR_INIT(reg_name, id, value)\ argument
128 REG_STRUCT[id].reg_name = value
130 #define SRI(reg_name, block, id)\ argument
131 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c103 #define SR(reg_name)\ argument
104 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
105 reg ## reg_name
106 #define SR_ARR(reg_name, id)\ argument
107 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
108 reg ## reg_name
109 #define SR_ARR_INIT(reg_name, id, value)\ argument
110 REG_STRUCT[id].reg_name = value
112 #define SRI(reg_name, block, id)\ argument
113 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn42/
H A Ddcn42_resource.c117 #define SR(reg_name) \ argument
118 REG_STRUCT.reg_name = BASE(reg##reg_name##_BASE_IDX) + \
119 reg##reg_name
120 #define SR_ARR(reg_name, id) \ argument
121 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \
122 reg##reg_name
123 #define SR_ARR_INIT(reg_name, id, value) \ argument
124 REG_STRUCT[id].reg_name = value
126 #define SRI(reg_name, block, id) \ argument
127 REG_STRUCT.reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c120 #define SR(reg_name)\ argument
121 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
122 reg ## reg_name
124 #define SR_ARR(reg_name, id) \ argument
125 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
127 #define SR_ARR_INIT(reg_name, id, value) \ argument
128 REG_STRUCT[id].reg_name = value
130 #define SRI(reg_name, block, id)\ argument
131 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
132 reg ## block ## id ## _ ## reg_name
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c135 #define SR(reg_name)\ argument
136 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
137 reg ## reg_name
139 #define SR_ARR(reg_name, id) \ argument
140 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
142 #define SR_ARR_INIT(reg_name, id, value) \ argument
143 REG_STRUCT[id].reg_name = value
145 #define SRI(reg_name, block, id)\ argument
146 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 reg ## block ## id ## _ ## reg_name
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c115 #define SR(reg_name)\ argument
116 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
117 reg ## reg_name
119 #define SR_ARR(reg_name, id) \ argument
120 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
122 #define SR_ARR_INIT(reg_name, id, value) \ argument
123 REG_STRUCT[id].reg_name = value
125 #define SRI(reg_name, block, id)\ argument
126 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
127 reg ## block ## id ## _ ## reg_name
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce110/
H A Dhw_factory_dce110.c42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
43 .field_name = reg_name ## __ ## field_name ## post_fix
45 #define REG(reg_name)\ argument
46 mm ## reg_name
48 #define REGI(reg_name, block, id)\ argument
49 mm ## block ## id ## _ ## reg_name
79 #define SF_DDC(reg_name, field_name, post_fix)\ argument
80 .field_name = reg_name ## __ ## field_name ## post_fix
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn42b/
H A Ddcn42b_resource.c182 #define SR(reg_name) \ argument
183 REG_STRUCT.reg_name = BASE(reg##reg_name##_BASE_IDX) + \
184 reg##reg_name
185 #define SR_ARR(reg_name, id) \ argument
186 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \
187 reg##reg_name
188 #define SR_ARR_INIT(reg_name, id, value) \ argument
189 REG_STRUCT[id].reg_name = value
191 #define SRI(reg_name, block, id) \ argument
192 REG_STRUCT.reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
[all …]
/linux/tools/testing/selftests/kvm/arm64/
H A Ddebug-exceptions.c40 #define GEN_DEBUG_WRITE_REG(reg_name) \ argument
41 static void write_##reg_name(int num, u64 val) \
45 write_sysreg(val, reg_name##0_el1); \
48 write_sysreg(val, reg_name##1_el1); \
51 write_sysreg(val, reg_name##2_el1); \
54 write_sysreg(val, reg_name##3_el1); \
57 write_sysreg(val, reg_name##4_el1); \
60 write_sysreg(val, reg_name##5_el1); \
63 write_sysreg(val, reg_name##6_el1); \
66 write_sysreg(val, reg_name##
[all...]
/linux/tools/lib/bpf/
H A Dusdt.c1297 static int calc_pt_regs_off(const char *reg_name) in calc_pt_regs_off() argument
1333 if (strcmp(reg_name, reg_map[i].names[j]) == 0) in calc_pt_regs_off()
1338 pr_warn("usdt: unrecognized register '%s'\n", reg_name); in calc_pt_regs_off()
1344 char reg_name[16] = {0}, idx_reg_name[16] = {0}; in parse_usdt_arg() local
1349 arg_sz, &off, reg_name, idx_reg_name, &scale, &len) == 5 || in parse_usdt_arg()
1351 arg_sz, reg_name, idx_reg_name, &scale, &len) == 4 || in parse_usdt_arg()
1353 arg_sz, &off, reg_name, idx_reg_name, &len) == 4 || in parse_usdt_arg()
1355 arg_sz, reg_name, idx_reg_name, &len) == 3 in parse_usdt_arg()
1367 reg_off = calc_pt_regs_off(reg_name); in parse_usdt_arg()
1388 arg_sz, &off, reg_name, &len) == 3) { in parse_usdt_arg()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h34 #define SR(reg_name)\ argument
35 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
36 mm ## reg_name
38 #define SRI(reg_name, block, id)\ argument
39 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
40 mm ## block ## id ## _ ## reg_name
43 #define SRII(reg_name, block, id)\ argument
44 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
45 mm ## block ## id ## _ ## reg_name
47 #define SF(reg_name, field_name, post_fix)\ argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c126 #define SR(reg_name)\ argument
127 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
128 reg ## reg_name
129 #define SR_ARR(reg_name, id) \ argument
130 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
132 #define SR_ARR_INIT(reg_name, id, value) \ argument
133 REG_STRUCT[id].reg_name = value
135 #define SRI(reg_name, block, id)\ argument
136 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
137 reg ## block ## id ## _ ## reg_name
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c172 #define NBIO_SR(reg_name)\ argument
173 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
174 mm ## reg_name
181 #define SR(reg_name)\ argument
182 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
184 #define SF(reg_name, field_name, post_fix)\ argument
185 .field_name = reg_name ## __ ## field_name ## post_fix
187 #define SRI(reg_name, block, id)\ argument
188 ….reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_…
190 #define SRI2(reg_name, block, id)\ argument
[all …]

123456