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Searched refs:reg_name (Results 1 – 25 of 287) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h37 #define REG_OFFSET(reg_name) (BASE(mm##reg_name##_BASE_IDX) + mm##reg_name) argument
39 #define FD_SHIFT(reg_name, field) reg_name##__##field##__SHIFT argument
41 #define FD_MASK(reg_name, field) reg_name##__##field##_MASK argument
47 #define FN(reg_name, field) FD(reg_name##__##field) argument
58 #define REG_SET_N(reg_name, n, initial_val, ...) \ argument
59 dmub_reg_set(CTX, REG(reg_name), initial_val, n, __VA_ARGS__)
61 #define REG_SET(reg_name, initial_val, field, val) \ argument
62 REG_SET_N(reg_name, 1, initial_val, \
63 FN(reg_name, field), val)
85 #define REG_UPDATE_N(reg_name, n, ...)\ argument
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H A Ddmub_dcn316.c43 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name) argument
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dreg_helper.h39 #define REG_READ(reg_name) \ argument
40 dm_read_reg(CTX, REG(reg_name))
42 #define REG_WRITE(reg_name, value) \ argument
43 dm_write_reg(CTX, REG(reg_name), value)
54 #define REG_SET_N(reg_name, n, initial_val, ...) \ argument
56 REG(reg_name), \
60 #define FN(reg_name, field) \ argument
61 FD(reg_name##__##field)
63 #define REG_SET(reg_name, initial_val, field, val) \ argument
64 REG_SET_N(reg_name, 1, initial_val, \
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/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
H A Dhw_factory_dcn21.c57 #define REG(reg_name)\ argument
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
60 #define SF_HPD(reg_name, field_name, post_fix)\ argument
61 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
63 #define REGI(reg_name, block, id)\ argument
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
65 mm ## block ## id ## _ ## reg_name
67 #define SF(reg_name, field_name, post_fix)\ argument
68 .field_name = reg_name ## __ ## field_name ## post_fix
99 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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/linux/tools/perf/util/
H A Dperf_regs.c35 const char *reg_name = NULL; in perf_reg_name() local
38 reg_name = __perf_reg_name_csky(id); in perf_reg_name()
40 reg_name = __perf_reg_name_loongarch(id); in perf_reg_name()
42 reg_name = __perf_reg_name_mips(id); in perf_reg_name()
44 reg_name = __perf_reg_name_powerpc(id); in perf_reg_name()
46 reg_name = __perf_reg_name_riscv(id); in perf_reg_name()
48 reg_name = __perf_reg_name_s390(id); in perf_reg_name()
50 reg_name = __perf_reg_name_x86(id); in perf_reg_name()
52 reg_name = __perf_reg_name_arm(id); in perf_reg_name()
54 reg_name = __perf_reg_name_arm64(id); in perf_reg_name()
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/linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/
H A Dhw_factory_dce120.c46 #define SF_HPD(reg_name, field_name, post_fix)\ argument
47 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
50 #define SF_HPD(reg_name, field_name, post_fix)\ argument
51 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
60 #define REG(reg_name)\ argument
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
63 #define REGI(reg_name, block, id)\ argument
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
65 mm ## block ## id ## _ ## reg_name
96 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
H A Dhw_factory_dcn32.c59 #define REG(reg_name)\ argument
60 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
63 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
65 #define REGI(reg_name, block, id)\ argument
66 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
67 reg ## block ## id ## _ ## reg_name
69 #define SF(reg_name, field_name, post_fix)\ argument
70 .field_name = reg_name ## __ ## field_name ## post_fix
101 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_factory_dcn30.c66 #define REG(reg_name)\ argument
67 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
69 #define SF_HPD(reg_name, field_name, post_fix)\ argument
70 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
72 #define REGI(reg_name, block, id)\ argument
73 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
74 mm ## block ## id ## _ ## reg_name
76 #define SF(reg_name, field_name, post_fix)\ argument
77 .field_name = reg_name ## __ ## field_name ## post_fix
109 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
H A Dhw_factory_dcn315.c63 #define REG(reg_name)\ argument
64 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
66 #define SF_HPD(reg_name, field_name, post_fix)\ argument
67 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
69 #define REGI(reg_name, block, id)\ argument
70 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
71 reg ## block ## id ## _ ## reg_name
73 #define SF(reg_name, field_name, post_fix)\ argument
74 .field_name = reg_name ## __ ## field_name ## post_fix
105 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
H A Dhw_factory_dcn20.c59 #define REG(reg_name)\ argument
60 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
63 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
65 #define REGI(reg_name, block, id)\ argument
66 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
67 mm ## block ## id ## _ ## reg_name
69 #define SF(reg_name, field_name, post_fix)\ argument
70 .field_name = reg_name ## __ ## field_name ## post_fix
102 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn401/
H A Dhw_factory_dcn401.c39 #define REG(reg_name)\ argument
40 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
43 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
45 #define REGI(reg_name, block, id)\ argument
46 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
47 reg ## block ## id ## _ ## reg_name
49 #define SF(reg_name, field_name, post_fix)\ argument
50 .field_name = reg_name ## __ ## field_name ## post_fix
81 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
H A Dhw_factory_dcn10.c47 #define SF_HPD(reg_name, field_name, post_fix)\ argument
48 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
57 #define REG(reg_name)\ argument
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
60 #define REGI(reg_name, block, id)\ argument
61 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
62 mm ## block ## id ## _ ## reg_name
92 #define SF_DDC(reg_name, field_name, post_fix)\ argument
93 .field_name = reg_name ## __ ## field_name ## post_fix
128 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_panel_cntl.h32 #define DCE_PANEL_CNTL_SR(reg_name, block)\ argument
33 .reg_name = mm ## block ## _ ## reg_name
45 #define DCN_PANEL_CNTL_SR(reg_name, block)\ argument
46 .reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \
47 mm ## block ## _ ## reg_name
59 #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\ argument
60 .field_name = reg_name ## __ ## field_name ## post_fix
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce110/
H A Dhw_factory_dce110.c42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
43 .field_name = reg_name ## __ ## field_name ## post_fix
45 #define REG(reg_name)\ argument
46 mm ## reg_name
48 #define REGI(reg_name, block, id)\ argument
49 mm ## block ## id ## _ ## reg_name
79 #define SF_DDC(reg_name, field_name, post_fix)\ argument
80 .field_name = reg_name ## __ ## field_name ## post_fix
/linux/tools/testing/selftests/kvm/aarch64/
H A Ddebug-exceptions.c40 #define GEN_DEBUG_WRITE_REG(reg_name) \ argument
41 static void write_##reg_name(int num, uint64_t val) \
45 write_sysreg(val, reg_name##0_el1); \
48 write_sysreg(val, reg_name##1_el1); \
51 write_sysreg(val, reg_name##2_el1); \
54 write_sysreg(val, reg_name##3_el1); \
57 write_sysreg(val, reg_name##4_el1); \
60 write_sysreg(val, reg_name##5_el1); \
63 write_sysreg(val, reg_name##6_el1); \
66 write_sysreg(val, reg_name##
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/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h34 #define SR(reg_name)\ argument
35 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
36 mm ## reg_name
38 #define SRI(reg_name, block, id)\ argument
39 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
40 mm ## block ## id ## _ ## reg_name
43 #define SRII(reg_name, block, id)\ argument
44 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
45 mm ## block ## id ## _ ## reg_name
47 #define SF(reg_name, field_name, post_fix)\ argument
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c251 #define SR(reg_name)\ argument
252 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
253 mm ## reg_name
255 #define SRI(reg_name, block, id)\ argument
256 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
257 mm ## block ## id ## _ ## reg_name
259 #define SRIR(var_name, reg_name, block, id)\ argument
260 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
261 mm ## block ## id ## _ ## reg_name
263 #define SRII(reg_name, block, id)\ argument
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.c64 #define REG(reg_name) \ argument
65 (MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
67 #define FN(reg_name, field) \ argument
68 FD(reg_name##__##field)
70 #define REG_NBIO(reg_name) \ argument
71 …(NBIO_BASE.instance[0].segment[regBIF_BX_PF2_ ## reg_name ## _BASE_IDX] + regBIF_BX_PF2_ ## reg_na…
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr_vbios_smu.c64 #define REG(reg_name) \ argument
65 (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
67 #define FN(reg_name, field) \ argument
68 FD(reg_name##__##field)
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_err.c1203 .reg_name = "SSU_BP_STATUS_0~5",
1207 .reg_name = "LO_PRI_UNICAST_CUR_CNT",
1211 .reg_name = "HI/LO_PRI_MULTICAST_CUR_CNT",
1215 .reg_name = "SSU_MB_RD_RLT_DROP_CNT",
1219 .reg_name = "SSU_PPP_MAC_KEY_NUM",
1223 .reg_name = "SSU_PPP_HOST_KEY_NUM",
1227 .reg_name = "PPP_SSU_MAC/HOST_RLT_NUM",
1231 .reg_name = "FULL/PART_DROP_NUM",
1235 .reg_name = "PPP_KEY/RLT_DROP_NUM",
1239 .reg_name = "NIC/ROC_L2_ERR_DROP_PKT_CNT",
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/linux/drivers/media/i2c/ccs/
H A Dccs-reg-access.h33 #define ccs_read(sensor, reg_name, val) \ argument
34 ccs_read_addr(sensor, CCS_R_##reg_name, val)
36 #define ccs_write(sensor, reg_name, val) \ argument
37 ccs_write_addr(sensor, CCS_R_##reg_name, val)
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c101 #define SR(reg_name)\ argument
102 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
103 mm ## reg_name
105 #define SRI(reg_name, block, id)\ argument
106 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
107 mm ## block ## id ## _ ## reg_name
109 #define SRIR(var_name, reg_name, block, id)\ argument
110 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
111 mm ## block ## id ## _ ## reg_name
113 #define SRII(reg_name, block, id)\ argument
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/linux/drivers/regulator/
H A Devent.c30 int reg_generate_netlink_event(const char *reg_name, u64 event) in reg_generate_netlink_event() argument
64 strscpy(edata->reg_name, reg_name, sizeof(edata->reg_name)); in reg_generate_netlink_event()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
H A Ddce112_clk_mgr.c37 #define SR(reg_name)\ argument
38 .reg_name = mm ## reg_name
41 #define SRI(reg_name, block, id)\ argument
42 .reg_name = mm ## block ## id ## _ ## reg_name
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr_vbios_smu.c40 #define REG(reg_name) \ argument
41 (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
43 #define FN(reg_name, field) \ argument
44 FD(reg_name##__##field)

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