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Searched refs:reg_enable (Results 1 – 4 of 4) sorted by relevance

/linux/tools/testing/selftests/user_events/
H A Dabi_test.c218 static int reg_enable(void *enable, int size, int bit) in reg_enable() function
264 ASSERT_EQ(0, reg_enable(&self->check, sizeof(int), 0)); in TEST_F()
304 ASSERT_EQ(0, reg_enable(&self->check, sizeof(int), 0)); in TEST_F()
305 ASSERT_EQ(0, reg_enable(&self->check, sizeof(int), 31)); in TEST_F()
306 ASSERT_NE(0, reg_enable(&self->check, sizeof(int), 32)); in TEST_F()
312 ASSERT_EQ(0, reg_enable(&self->check_long, sizeof(long), 63)); in TEST_F()
313 ASSERT_NE(0, reg_enable(&self->check_long, sizeof(long), 64)); in TEST_F()
318 ASSERT_NE(0, reg_enable(&self->check, 1, 0)); in TEST_F()
319 ASSERT_NE(0, reg_enable(&self->check, 2, 0)); in TEST_F()
320 ASSERT_NE(0, reg_enable(&self->check, 3, 0)); in TEST_F()
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/linux/drivers/irqchip/
H A Dirq-bcm6345-l1.c90 static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc, in reg_enable() function
131 pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx)); in bcm6345_l1_irq_handle()
151 intc->cpus[cpu_idx]->map_base + reg_enable(intc, word)); in __bcm6345_l1_unmask()
163 intc->cpus[cpu_idx]->map_base + reg_enable(intc, word)); in __bcm6345_l1_mask()
255 __raw_writel(0, cpu->map_base + reg_enable(intc, i)); in bcm6345_l1_init_one()
H A Dirq-bcm2835.c70 static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 }; variable
154 intc.enable[b] = base + reg_enable[b]; in armctrl_of_init()
/linux/arch/arm64/kernel/
H A Dhw_breakpoint.c230 int i, max_slots, ctrl_reg, val_reg, reg_enable; in hw_breakpoint_control() local
240 reg_enable = !debug_info->bps_disabled; in hw_breakpoint_control()
247 reg_enable = !debug_info->wps_disabled; in hw_breakpoint_control()
270 reg_enable ? ctrl | 0x1 : ctrl & ~0x1); in hw_breakpoint_control()