Searched refs:reg_block (Results 1 – 4 of 4) sorted by relevance
193 idx += gctx->reg_block; in atom_get_src_int()263 val = gctx->reg_block; in atom_get_src_int()471 idx += gctx->reg_block; in atom_put_dst()537 gctx->reg_block = val; in atom_put_dst()895 ctx->ctx->reg_block = U16(*ptr); in atom_op_setregblock()897 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); in atom_op_setregblock()1242 ctx->reg_block = 0; in atom_execute_table_scratch_unlocked()
137 uint16_t reg_block; member
3997 ATOM_INIT_REG_BLOCK *reg_block = in radeon_atom_init_mc_reg_table() local4002 ((u8 *)reg_block + (2 * sizeof(u16)) + in radeon_atom_init_mc_reg_table()4003 le16_to_cpu(reg_block->usRegIndexTblSize)); in radeon_atom_init_mc_reg_table()4004 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; in radeon_atom_init_mc_reg_table()4005 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / in radeon_atom_init_mc_reg_table()4042 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); in radeon_atom_init_mc_reg_table()
485 u32 reg_block = 0; in i40e_pre_tx_queue_cfg() local489 reg_block = abs_queue_idx / 128; in i40e_pre_tx_queue_cfg()493 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); in i40e_pre_tx_queue_cfg()502 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); in i40e_pre_tx_queue_cfg()809 u32 reg_block = 0; in i40e_clear_hw() local812 reg_block = abs_queue_idx / 128; in i40e_clear_hw()816 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); in i40e_clear_hw()821 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); in i40e_clear_hw()