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Searched refs:reg_bit (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/net/ipa/
H A Dipa_table.c367 val = reg_bit(reg, IPV6_ROUTER_HASH); in ipa_table_hash_flush()
368 val |= reg_bit(reg, IPV6_FILTER_HASH); in ipa_table_hash_flush()
369 val |= reg_bit(reg, IPV4_ROUTER_HASH); in ipa_table_hash_flush()
370 val |= reg_bit(reg, IPV4_FILTER_HASH); in ipa_table_hash_flush()
375 val = reg_bit(reg, ROUTER_CACHE); in ipa_table_hash_flush()
376 val |= reg_bit(reg, FILTER_CACHE); in ipa_table_hash_flush()
H A Dipa_endpoint.c470 mask = reg_bit(reg, field_id); in ipa_endpoint_init_ctrl()
814 val |= reg_bit(reg, HDR_OFST_PKT_SIZE_VALID); in ipa_endpoint_init_hdr()
818 val |= reg_bit(reg, HDR_OFST_METADATA_VALID); in ipa_endpoint_init_hdr()
840 val |= reg_bit(reg, HDR_ENDIANNESS); /* big endian */ in ipa_endpoint_init_hdr_ext()
850 val |= reg_bit(reg, HDR_TOTAL_LEN_OR_PAD_VALID); in ipa_endpoint_init_hdr_ext()
852 val |= reg_bit(reg, HDR_PAYLOAD_LEN_INC_PADDING); in ipa_endpoint_init_hdr_ext()
1025 val |= reg_bit(reg, SW_EOF_ACTIVE); in ipa_endpoint_init_aggr()
1136 val = enable ? reg_bit(reg, HOL_BLOCK_EN) : 0; in ipa_endpoint_init_hol_block_en()
1281 val |= reg_bit(reg, STATUS_EN); in ipa_endpoint_status()
1647 val |= reg_bit(reg, ROUTE_DEF_HDR_TABLE); in ipa_endpoint_default_route_set()
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H A Dreg.h83 static inline u32 reg_bit(const struct reg *reg, u32 field_id) in reg_bit() function
H A Dgsi.c727 val |= reg_bit(reg, EV_INTYPE); in gsi_evt_ring_program()
840 val |= reg_bit(reg, CHTYPE_DIR); in gsi_channel_program()
875 val |= reg_bit(reg, USE_DB_ENG); in gsi_channel_program()
883 val |= reg_bit(reg, USE_ESCAPE_BUF_ONLY); in gsi_channel_program()
889 val |= reg_bit(reg, DB_IN_BYTES); in gsi_channel_program()
1970 iowrite32(reg_bit(reg, INTYPE), gsi->virt + reg_offset(reg)); in gsi_irq_setup()
2074 if (!(val & reg_bit(reg, ENABLED))) { in gsi_setup()
/linux/drivers/pci/controller/
H A Dpcie-rzg3s-host.c510 u8 reg_bit = bit % RZG3S_PCI_MSI_INT_PER_REG; in rzg3s_pcie_msi_irq() local
514 writel_relaxed(BIT(reg_bit), in rzg3s_pcie_msi_irq()
526 u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; in rzg3s_pcie_msi_irq_ack() local
531 writel_relaxed(BIT(reg_bit), host->axi + RZG3S_PCI_MSIRS(reg_id)); in rzg3s_pcie_msi_irq_ack()
538 u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; in rzg3s_pcie_msi_irq_mask() local
543 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit), in rzg3s_pcie_msi_irq_mask()
544 BIT(reg_bit)); in rzg3s_pcie_msi_irq_mask()
551 u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; in rzg3s_pcie_msi_irq_unmask() local
556 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit), in rzg3s_pcie_msi_irq_unmask()
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_main.c3837 u32 val, reg, reg_bit; in hclge_reset_wait() local
3843 reg_bit = HCLGE_IMP_RESET_BIT; in hclge_reset_wait()
3847 reg_bit = HCLGE_GLOBAL_RESET_BIT; in hclge_reset_wait()
3851 reg_bit = HCLGE_FUN_RST_ING_B; in hclge_reset_wait()
3861 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { in hclge_reset_wait()