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Searched refs:reg_access_ctrl (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_virt.c1422 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in amdgpu_virt_rlcg_vfi_reg_rw() local
1452 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; in amdgpu_virt_rlcg_vfi_reg_rw()
1453 vfi_cmd = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_cmd; in amdgpu_virt_rlcg_vfi_reg_rw()
1454 vfi_stat = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_stat; in amdgpu_virt_rlcg_vfi_reg_rw()
1455 vfi_addr = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_addr; in amdgpu_virt_rlcg_vfi_reg_rw()
1456 vfi_data = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_data; in amdgpu_virt_rlcg_vfi_reg_rw()
1457 vfi_grbm_cntl = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_grbm_cntl; in amdgpu_virt_rlcg_vfi_reg_rw()
1458 vfi_grbm_idx = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_grbm_idx; in amdgpu_virt_rlcg_vfi_reg_rw()
1459 grbm_cntl_data = reg_access_ctrl->vfi_grbm_cntl_data; in amdgpu_virt_rlcg_vfi_reg_rw()
1460 grbm_idx_data = reg_access_ctrl->vfi_grbm_idx_data; in amdgpu_virt_rlcg_vfi_reg_rw()
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H A Dgfx_v12_1.c651 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v12_1_init_rlcg_reg_access_ctrl() local
655 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; in gfx_v12_1_init_rlcg_reg_access_ctrl()
657 reg_access_ctrl->grbm_cntl = in gfx_v12_1_init_rlcg_reg_access_ctrl()
659 reg_access_ctrl->grbm_idx = in gfx_v12_1_init_rlcg_reg_access_ctrl()
662 reg_access_ctrl->vfi_cmd = in gfx_v12_1_init_rlcg_reg_access_ctrl()
664 reg_access_ctrl->vfi_stat = in gfx_v12_1_init_rlcg_reg_access_ctrl()
666 reg_access_ctrl->vfi_addr = in gfx_v12_1_init_rlcg_reg_access_ctrl()
668 reg_access_ctrl->vfi_data = in gfx_v12_1_init_rlcg_reg_access_ctrl()
670 reg_access_ctrl->vfi_grbm_cntl = in gfx_v12_1_init_rlcg_reg_access_ctrl()
672 reg_access_ctrl->vfi_grbm_idx = in gfx_v12_1_init_rlcg_reg_access_ctrl()
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H A Dgfx_v9_4_3.c1373 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v9_4_3_init_rlcg_reg_access_ctrl() local
1377 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1378 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1379 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1380 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1381 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1382 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1383 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1384 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
H A Dgfx_v12_0.c741 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v12_0_init_rlcg_reg_access_ctrl() local
743 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v12_0_init_rlcg_reg_access_ctrl()
744 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v12_0_init_rlcg_reg_access_ctrl()
745 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); in gfx_v12_0_init_rlcg_reg_access_ctrl()
746 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v12_0_init_rlcg_reg_access_ctrl()
747 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); in gfx_v12_0_init_rlcg_reg_access_ctrl()
748 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v12_0_init_rlcg_reg_access_ctrl()
749 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v12_0_init_rlcg_reg_access_ctrl()
750 reg_access_ctrl in gfx_v12_0_init_rlcg_reg_access_ctrl()
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H A Dgfx_v9_0.c1823 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v9_0_init_rlcg_reg_access_ctrl() local
1825 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v9_0_init_rlcg_reg_access_ctrl()
1826 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1827 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1828 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1829 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1830 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1831 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1832 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); in gfx_v9_0_init_rlcg_reg_access_ctrl()
H A Dgfx_v11_0.c912 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v11_0_init_rlcg_reg_access_ctrl() local
914 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v11_0_init_rlcg_reg_access_ctrl()
915 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
916 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); in gfx_v11_0_init_rlcg_reg_access_ctrl()
917 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v11_0_init_rlcg_reg_access_ctrl()
918 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); in gfx_v11_0_init_rlcg_reg_access_ctrl()
919 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_init_rlcg_reg_access_ctrl()
920 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v11_0_init_rlcg_reg_access_ctrl()
921 reg_access_ctrl in gfx_v11_0_init_rlcg_reg_access_ctrl()
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H A Dgfx_v10_0.c4361 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v10_0_init_rlcg_reg_access_ctrl() local
4363 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v10_0_init_rlcg_reg_access_ctrl()
4364 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4365 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4366 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4367 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4368 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4369 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4372 reg_access_ctrl->spare_int = in gfx_v10_0_init_rlcg_reg_access_ctrl()
4376 reg_access_ctrl->spare_int = in gfx_v10_0_init_rlcg_reg_access_ctrl()