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Searched refs:reg_access_ctrl (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_virt.c1011 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in amdgpu_virt_rlcg_reg_rw() local
1035 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; in amdgpu_virt_rlcg_reg_rw()
1036 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; in amdgpu_virt_rlcg_reg_rw()
1037 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; in amdgpu_virt_rlcg_reg_rw()
1038 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; in amdgpu_virt_rlcg_reg_rw()
1039 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; in amdgpu_virt_rlcg_reg_rw()
1043 if (reg_access_ctrl->spare_int) in amdgpu_virt_rlcg_reg_rw()
1044 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int; in amdgpu_virt_rlcg_reg_rw()
1046 if (offset == reg_access_ctrl->grbm_cntl) { in amdgpu_virt_rlcg_reg_rw()
1051 } else if (offset == reg_access_ctrl->grbm_idx) { in amdgpu_virt_rlcg_reg_rw()
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H A Damdgpu_rlc.h336 struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl[AMDGPU_MAX_RLC_INSTANCES]; member
H A Dgfx_v9_4_3.c1417 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v9_4_3_init_rlcg_reg_access_ctrl() local
1421 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1422 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1423 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1424 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1425 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1426 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1427 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1428 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
H A Dgfx_v12_0.c693 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v12_0_init_rlcg_reg_access_ctrl() local
695 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v12_0_init_rlcg_reg_access_ctrl()
696 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v12_0_init_rlcg_reg_access_ctrl()
697 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); in gfx_v12_0_init_rlcg_reg_access_ctrl()
698 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v12_0_init_rlcg_reg_access_ctrl()
699 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); in gfx_v12_0_init_rlcg_reg_access_ctrl()
700 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v12_0_init_rlcg_reg_access_ctrl()
701 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v12_0_init_rlcg_reg_access_ctrl()
702 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v12_0_init_rlcg_reg_access_ctrl()
H A Dgfx_v11_0.c871 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v11_0_init_rlcg_reg_access_ctrl() local
873 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v11_0_init_rlcg_reg_access_ctrl()
874 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
875 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); in gfx_v11_0_init_rlcg_reg_access_ctrl()
876 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v11_0_init_rlcg_reg_access_ctrl()
877 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); in gfx_v11_0_init_rlcg_reg_access_ctrl()
878 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_init_rlcg_reg_access_ctrl()
879 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v11_0_init_rlcg_reg_access_ctrl()
880 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
H A Dgfx_v9_0.c1811 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v9_0_init_rlcg_reg_access_ctrl() local
1813 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v9_0_init_rlcg_reg_access_ctrl()
1814 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1815 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1816 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1817 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1818 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1819 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1820 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); in gfx_v9_0_init_rlcg_reg_access_ctrl()
H A Dgfx_v10_0.c4301 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v10_0_init_rlcg_reg_access_ctrl() local
4303 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v10_0_init_rlcg_reg_access_ctrl()
4304 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4305 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4306 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4307 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4308 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4309 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4312 reg_access_ctrl->spare_int = in gfx_v10_0_init_rlcg_reg_access_ctrl()
4316 reg_access_ctrl->spare_int = in gfx_v10_0_init_rlcg_reg_access_ctrl()