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Searched refs:regVPG5_VPG_MEM_PWR (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h12267 #define regVPG5_VPG_MEM_PWR … macro
H A Ddcn_3_1_5_offset.h12836 #define regVPG5_VPG_MEM_PWR … macro
H A Ddcn_3_5_1_offset.h13269 #define regVPG5_VPG_MEM_PWR … macro
H A Ddcn_3_5_0_offset.h13290 #define regVPG5_VPG_MEM_PWR … macro
H A Ddcn_3_1_4_offset.h12438 #define regVPG5_VPG_MEM_PWR … macro
H A Ddcn_3_1_2_offset.h12973 #define regVPG5_VPG_MEM_PWR … macro
H A Ddcn_3_2_1_offset.h12251 #define regVPG5_VPG_MEM_PWR … macro
H A Ddcn_3_1_6_offset.h13569 #define regVPG5_VPG_MEM_PWR … macro
H A Ddcn_4_1_0_offset.h12994 #define regVPG5_VPG_MEM_PWR … macro