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Searched refs:regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h12270 #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12839 #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h13272 #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h13293 #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h12441 #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h12976 #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h12254 #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13572 #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h12997 #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX … macro