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Searched refs:regVCN_RB_ENABLE (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_2.c652 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_2_start_dpg_mode()
654 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_2_start_dpg_mode()
660 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_2_start_dpg_mode()
662 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_2_start_dpg_mode()
805 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_2_start()
807 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_2_start()
816 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_2_start()
818 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_2_start()
H A Dumsch_mm_v4_0.c235 data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE); in umsch_mm_v4_0_ring_start()
237 WREG32_SOC15(VCN, 0, regVCN_RB_ENABLE, data); in umsch_mm_v4_0_ring_start()
250 data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE); in umsch_mm_v4_0_ring_stop()
252 WREG32_SOC15(VCN, 0, regVCN_RB_ENABLE, data); in umsch_mm_v4_0_ring_stop()
H A Dvcn_v5_0_0.c770 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v5_0_0_start_dpg_mode()
772 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start_dpg_mode()
781 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v5_0_0_start_dpg_mode()
783 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start_dpg_mode()
931 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v5_0_0_start()
933 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start()
942 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v5_0_0_start()
944 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start()
H A Dvcn_v4_0_5.c1013 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_5_start_dpg_mode()
1015 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start_dpg_mode()
1024 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_5_start_dpg_mode()
1026 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start_dpg_mode()
1203 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_5_start()
1205 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start()
1214 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_5_start()
1216 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start()
1221 RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_5_start()
H A Dvcn_v5_0_1.c756 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_1_start_dpg_mode()
758 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_1_start_dpg_mode()
767 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_1_start_dpg_mode()
769 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_1_start_dpg_mode()
1101 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_1_start()
1103 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_1_start()
1112 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_1_start()
1114 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_1_start()
H A Dvcn_v4_0_3.c985 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start_dpg_mode()
987 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start_dpg_mode()
995 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start_dpg_mode()
997 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start_dpg_mode()
1352 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start()
1354 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start()
1360 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start()
1362 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start()
H A Dvcn_v4_0.c1100 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_start_dpg_mode()
1102 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start_dpg_mode()
1111 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_start_dpg_mode()
1113 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start_dpg_mode()
1290 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_start()
1292 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start()
1301 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_start()
1303 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_5_0_0_offset.h1120 #define regVCN_RB_ENABLE … macro
H A Dvcn_4_0_5_offset.h1289 #define regVCN_RB_ENABLE … macro
H A Dvcn_4_0_0_offset.h1334 #define regVCN_RB_ENABLE … macro