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Searched refs:regVCN_RB_ENABLE (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_1.c539 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_1_start_dpg_mode()
541 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_1_start_dpg_mode()
550 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_1_start_dpg_mode()
552 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_1_start_dpg_mode()
698 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_1_start()
700 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_1_start()
709 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_1_start()
711 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_1_start()
H A Dumsch_mm_v4_0.c235 data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE); in umsch_mm_v4_0_ring_start()
237 WREG32_SOC15(VCN, 0, regVCN_RB_ENABLE, data); in umsch_mm_v4_0_ring_start()
250 data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE); in umsch_mm_v4_0_ring_stop()
252 WREG32_SOC15(VCN, 0, regVCN_RB_ENABLE, data); in umsch_mm_v4_0_ring_stop()
H A Dvcn_v5_0_0.c743 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v5_0_0_start_dpg_mode()
745 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start_dpg_mode()
754 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v5_0_0_start_dpg_mode()
756 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start_dpg_mode()
902 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v5_0_0_start()
904 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start()
913 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v5_0_0_start()
915 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start()
H A Dvcn_v4_0_5.c965 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_5_start_dpg_mode()
967 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start_dpg_mode()
976 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_5_start_dpg_mode()
978 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start_dpg_mode()
1154 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_5_start()
1156 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start()
1165 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_5_start()
1167 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start()
H A Dvcn_v4_0_3.c902 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start_dpg_mode()
904 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start_dpg_mode()
912 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start_dpg_mode()
914 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start_dpg_mode()
1270 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start()
1272 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start()
1278 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start()
1280 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start()
H A Dvcn_v4_0.c1062 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_start_dpg_mode()
1064 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start_dpg_mode()
1073 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_start_dpg_mode()
1075 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start_dpg_mode()
1250 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_start()
1252 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start()
1261 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_start()
1263 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_5_0_0_offset.h1114 #define regVCN_RB_ENABLE … macro
H A Dvcn_4_0_5_offset.h1289 #define regVCN_RB_ENABLE … macro
H A Dvcn_4_0_0_offset.h1334 #define regVCN_RB_ENABLE … macro
H A Dvcn_4_0_3_offset.h1236 #define regVCN_RB_ENABLE … macro