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Searched refs:regVCN_RB_ENABLE (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dumsch_mm_v4_0.c235 data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE); in umsch_mm_v4_0_ring_start()
237 WREG32_SOC15(VCN, 0, regVCN_RB_ENABLE, data); in umsch_mm_v4_0_ring_start()
250 data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE); in umsch_mm_v4_0_ring_stop()
252 WREG32_SOC15(VCN, 0, regVCN_RB_ENABLE, data); in umsch_mm_v4_0_ring_stop()
H A Dvcn_v5_0_0.c729 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v5_0_0_start_dpg_mode()
731 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start_dpg_mode()
740 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v5_0_0_start_dpg_mode()
742 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start_dpg_mode()
886 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v5_0_0_start()
888 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start()
897 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v5_0_0_start()
899 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start()
H A Dvcn_v4_0_5.c967 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_5_start_dpg_mode()
969 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start_dpg_mode()
978 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_5_start_dpg_mode()
980 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start_dpg_mode()
1154 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_5_start()
1156 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start()
1165 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_5_start()
1167 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start()
H A Dvcn_v4_0_3.c874 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start_dpg_mode()
876 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start_dpg_mode()
884 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start_dpg_mode()
886 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start_dpg_mode()
1238 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start()
1240 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start()
1246 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start()
1248 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start()
H A Dvcn_v4_0.c1055 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_start_dpg_mode()
1057 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start_dpg_mode()
1066 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_start_dpg_mode()
1068 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start_dpg_mode()
1241 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_start()
1243 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start()
1252 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_start()
1254 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_5_0_0_offset.h1114 #define regVCN_RB_ENABLE … macro
H A Dvcn_4_0_5_offset.h1289 #define regVCN_RB_ENABLE … macro
H A Dvcn_4_0_0_offset.h1334 #define regVCN_RB_ENABLE … macro
H A Dvcn_4_0_3_offset.h1236 #define regVCN_RB_ENABLE … macro