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Searched refs:regVCN_RB1_DB_CTRL (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_1.c555 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, in vcn_v5_0_1_start_dpg_mode()
559 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); in vcn_v5_0_1_start_dpg_mode()
687 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, in vcn_v5_0_1_start()
692 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); in vcn_v5_0_1_start()
H A Dvcn_v5_0_0.c759 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, in vcn_v5_0_0_start_dpg_mode()
894 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, in vcn_v5_0_0_start()
H A Dvcn_v4_0_5.c981 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, in vcn_v4_0_5_start_dpg_mode()
1146 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, in vcn_v4_0_5_start()
H A Dvcn_v4_0_3.c313 regVCN_RB1_DB_CTRL, in vcn_v4_0_3_hw_init()
321 regVCN_RB1_DB_CTRL); in vcn_v4_0_3_hw_init()
H A Dvcn_v4_0.c1078 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, in vcn_v4_0_start_dpg_mode()
1242 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, in vcn_v4_0_start()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_5_0_0_offset.h1078 #define regVCN_RB1_DB_CTRL … macro
H A Dvcn_4_0_5_offset.h1255 #define regVCN_RB1_DB_CTRL … macro
H A Dvcn_4_0_0_offset.h1300 #define regVCN_RB1_DB_CTRL … macro
H A Dvcn_4_0_3_offset.h1228 #define regVCN_RB1_DB_CTRL … macro