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Searched refs:regUVD_VCPU_NONCACHE_OFFSET0 (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c381 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); in vcn_v5_0_0_mc_resume()
484 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
H A Dvcn_v4_0_5.c417 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); in vcn_v4_0_5_mc_resume()
525 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
H A Dvcn_v4_0_3.c437 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); in vcn_v4_0_3_mc_resume()
545 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
H A Dvcn_v4_0.c469 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); in vcn_v4_0_mc_resume()
571 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h66 #define regUVD_VCPU_NONCACHE_OFFSET0 … macro
H A Dvcn_5_0_0_offset.h404 #define regUVD_VCPU_NONCACHE_OFFSET0 … macro
H A Dvcn_4_0_5_offset.h397 #define regUVD_VCPU_NONCACHE_OFFSET0 … macro
H A Dvcn_4_0_0_offset.h414 #define regUVD_VCPU_NONCACHE_OFFSET0 … macro
H A Dvcn_4_0_3_offset.h416 #define regUVD_VCPU_NONCACHE_OFFSET0 … macro