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Searched refs:regUVD_VCPU_INT_EN2 (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_5_0_0_offset.h320 #define regUVD_VCPU_INT_EN2 … macro
H A Dvcn_4_0_5_offset.h327 #define regUVD_VCPU_INT_EN2 … macro
H A Dvcn_4_0_0_offset.h340 #define regUVD_VCPU_INT_EN2 … macro
H A Dvcn_4_0_3_offset.h342 #define regUVD_VCPU_INT_EN2 … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c2034 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_VCPU_INT_EN2), in vcn_v4_0_3_enable_ras()