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Searched refs:regUVD_VCPU_CACHE_SIZE5_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h53 #define regUVD_VCPU_CACHE_SIZE5_BASE_IDX … macro
H A Dvcn_5_0_0_offset.h391 #define regUVD_VCPU_CACHE_SIZE5_BASE_IDX … macro
H A Dvcn_4_0_5_offset.h384 #define regUVD_VCPU_CACHE_SIZE5_BASE_IDX … macro
H A Dvcn_4_0_0_offset.h401 #define regUVD_VCPU_CACHE_SIZE5_BASE_IDX … macro
H A Dvcn_4_0_3_offset.h403 #define regUVD_VCPU_CACHE_SIZE5_BASE_IDX … macro