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Searched refs:regUVD_VCPU_CACHE_SIZE1 (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c416 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, in vcn_v4_0_3_mc_resume()
521 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
983 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_3_start_sriov()
H A Dvcn_v4_0.c454 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_mc_resume()
549 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1378 regUVD_VCPU_CACHE_SIZE1), in vcn_v4_0_start_sriov()
H A Dvcn_v5_0_0.c366 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v5_0_0_mc_resume()
462 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
H A Dvcn_v4_0_5.c402 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_5_mc_resume()
501 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h36 #define regUVD_VCPU_CACHE_SIZE1 … macro
H A Dvcn_5_0_0_offset.h374 #define regUVD_VCPU_CACHE_SIZE1 … macro
H A Dvcn_4_0_5_offset.h367 #define regUVD_VCPU_CACHE_SIZE1 … macro
H A Dvcn_4_0_0_offset.h384 #define regUVD_VCPU_CACHE_SIZE1 … macro
H A Dvcn_4_0_3_offset.h386 #define regUVD_VCPU_CACHE_SIZE1 … macro