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Searched refs:regUVD_VCPU_CACHE_SIZE0 (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_1.c291 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); in vcn_v5_0_1_mc_resume()
373 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
376 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
H A Dvcn_v5_0_0.c372 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); in vcn_v5_0_0_mc_resume()
452 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
455 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
H A Dvcn_v4_0_3.c436 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); in vcn_v4_0_3_mc_resume()
525 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
528 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
1002 regUVD_VCPU_CACHE_SIZE0), in vcn_v4_0_3_start_sriov()
H A Dvcn_v4_0_5.c392 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); in vcn_v4_0_5_mc_resume()
474 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
477 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
H A Dvcn_v4_0.c453 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); in vcn_v4_0_mc_resume()
532 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
535 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1373 regUVD_VCPU_CACHE_SIZE0), in vcn_v4_0_start_sriov()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h32 #define regUVD_VCPU_CACHE_SIZE0 … macro
H A Dvcn_5_0_0_offset.h370 #define regUVD_VCPU_CACHE_SIZE0 … macro
H A Dvcn_4_0_5_offset.h363 #define regUVD_VCPU_CACHE_SIZE0 … macro
H A Dvcn_4_0_0_offset.h380 #define regUVD_VCPU_CACHE_SIZE0 … macro
H A Dvcn_4_0_3_offset.h382 #define regUVD_VCPU_CACHE_SIZE0 … macro