Searched refs:regUVD_VCPU_CACHE_OFFSET2 (Results 1 – 10 of 10) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vcn_v5_0_1.c | 306 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v5_0_1_mc_resume()
409 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
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| H A D | vcn_v4_0_3.c | 454 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v4_0_3_mc_resume()
561 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
1025 regUVD_VCPU_CACHE_OFFSET2), 0); in vcn_v4_0_3_start_sriov()
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| H A D | vcn_v5_0_0.c | 387 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v5_0_0_mc_resume()
486 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
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| H A D | vcn_v4_0.c | 468 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v4_0_mc_resume()
566 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1399 regUVD_VCPU_CACHE_OFFSET2), in vcn_v4_0_start_sriov()
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| H A D | vcn_v4_0_5.c | 407 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v4_0_5_mc_resume()
511 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_2_6_0_offset.h | 38 #define regUVD_VCPU_CACHE_OFFSET2 … macro
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| H A D | vcn_5_0_0_offset.h | 376 #define regUVD_VCPU_CACHE_OFFSET2 … macro
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| H A D | vcn_4_0_5_offset.h | 369 #define regUVD_VCPU_CACHE_OFFSET2 … macro
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| H A D | vcn_4_0_0_offset.h | 386 #define regUVD_VCPU_CACHE_OFFSET2 … macro
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| H A D | vcn_4_0_3_offset.h | 388 #define regUVD_VCPU_CACHE_OFFSET2 … macro
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