Searched refs:regUVD_VCPU_CACHE_OFFSET1 (Results 1 – 10 of 10) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vcn_v5_0_1.c | 298 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v5_0_1_mc_resume()
387 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
394 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
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| H A D | vcn_v5_0_0.c | 379 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v5_0_0_mc_resume()
466 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
473 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
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| H A D | vcn_v4_0_3.c | 443 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v4_0_3_mc_resume()
539 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
546 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
1011 regUVD_VCPU_CACHE_OFFSET1), 0); in vcn_v4_0_3_start_sriov()
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| H A D | vcn_v4_0_5.c | 399 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v4_0_5_mc_resume()
488 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
495 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
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| H A D | vcn_v4_0.c | 460 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v4_0_mc_resume()
546 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
553 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1384 regUVD_VCPU_CACHE_OFFSET1), in vcn_v4_0_start_sriov()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_2_6_0_offset.h | 34 #define regUVD_VCPU_CACHE_OFFSET1 … macro
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| H A D | vcn_5_0_0_offset.h | 372 #define regUVD_VCPU_CACHE_OFFSET1 … macro
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| H A D | vcn_4_0_5_offset.h | 365 #define regUVD_VCPU_CACHE_OFFSET1 … macro
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| H A D | vcn_4_0_0_offset.h | 382 #define regUVD_VCPU_CACHE_OFFSET1 … macro
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| H A D | vcn_4_0_3_offset.h | 384 #define regUVD_VCPU_CACHE_OFFSET1 … macro
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