Home
last modified time | relevance | path

Searched refs:regUVD_VCPU_CACHE_OFFSET0_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h31 #define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX … macro
H A Dvcn_5_0_0_offset.h369 #define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX … macro
H A Dvcn_4_0_5_offset.h362 #define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX … macro
H A Dvcn_4_0_0_offset.h379 #define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX … macro
H A Dvcn_4_0_3_offset.h381 #define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX … macro