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Searched refs:regUVD_SUVD_CGC_CTRL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c732 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
743 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); in vcn_v4_0_5_disable_clock_gating()
800 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v4_0_5_disable_clock_gating_dpg_mode()
848 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); in vcn_v4_0_5_enable_clock_gating()
859 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); in vcn_v4_0_5_enable_clock_gating()
H A Dvcn_v4_0_3.c666 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); in vcn_v4_0_3_disable_clock_gating()
675 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); in vcn_v4_0_3_disable_clock_gating()
726 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
768 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); in vcn_v4_0_3_enable_clock_gating()
777 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); in vcn_v4_0_3_enable_clock_gating()
H A Dvcn_v4_0.c805 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); in vcn_v4_0_disable_clock_gating()
816 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); in vcn_v4_0_disable_clock_gating()
873 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
921 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); in vcn_v4_0_enable_clock_gating()
932 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); in vcn_v4_0_enable_clock_gating()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1256 #define regUVD_SUVD_CGC_CTRL … macro
H A Dvcn_5_0_0_offset.h128 #define regUVD_SUVD_CGC_CTRL … macro
H A Dvcn_4_0_5_offset.h149 #define regUVD_SUVD_CGC_CTRL … macro
H A Dvcn_4_0_0_offset.h150 #define regUVD_SUVD_CGC_CTRL … macro
H A Dvcn_4_0_3_offset.h150 #define regUVD_SUVD_CGC_CTRL … macro