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Searched refs:regUVD_SOFT_RESET (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c799 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); in vcn_v5_0_0_start()
802 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); in vcn_v5_0_0_start()
999 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); in vcn_v5_0_0_stop()
1001 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); in vcn_v5_0_0_stop()
1002 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); in vcn_v5_0_0_stop()
1004 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); in vcn_v5_0_0_stop()
H A Dvcn_v4_0_5.c1041 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); in vcn_v4_0_5_start()
1044 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); in vcn_v4_0_5_start()
1265 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); in vcn_v4_0_5_stop()
1267 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); in vcn_v4_0_5_stop()
1268 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); in vcn_v4_0_5_stop()
1270 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); in vcn_v4_0_5_stop()
H A Dvcn_v4_0_3.c1127 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); in vcn_v4_0_3_start()
1130 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); in vcn_v4_0_3_start()
1355 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); in vcn_v4_0_3_stop()
1357 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); in vcn_v4_0_3_stop()
1359 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); in vcn_v4_0_3_stop()
1361 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); in vcn_v4_0_3_stop()
H A Dvcn_v4_0.c1129 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); in vcn_v4_0_start()
1132 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); in vcn_v4_0_start()
1602 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); in vcn_v4_0_stop()
1604 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); in vcn_v4_0_stop()
1605 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); in vcn_v4_0_stop()
1607 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); in vcn_v4_0_stop()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1236 #define regUVD_SOFT_RESET … macro
H A Dvcn_5_0_0_offset.h338 #define regUVD_SOFT_RESET … macro
H A Dvcn_4_0_5_offset.h341 #define regUVD_SOFT_RESET … macro
H A Dvcn_4_0_0_offset.h358 #define regUVD_SOFT_RESET … macro
H A Dvcn_4_0_3_offset.h360 #define regUVD_SOFT_RESET … macro