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Searched refs:regUVD_RB_WPTR (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_1.c544 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); in vcn_v5_0_1_start_dpg_mode()
547 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp); in vcn_v5_0_1_start_dpg_mode()
548 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); in vcn_v5_0_1_start_dpg_mode()
703 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); in vcn_v5_0_1_start()
706 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp); in vcn_v5_0_1_start()
707 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); in vcn_v5_0_1_start()
738 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); in vcn_v5_0_1_stop_dpg_mode()
859 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR); in vcn_v5_0_1_unified_ring_get_wptr()
880 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, in vcn_v5_0_1_unified_ring_set_wptr()
H A Dvcn_v5_0_0.c57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
748 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); in vcn_v5_0_0_start_dpg_mode()
751 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); in vcn_v5_0_0_start_dpg_mode()
752 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); in vcn_v5_0_0_start_dpg_mode()
907 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); in vcn_v5_0_0_start()
910 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); in vcn_v5_0_0_start()
911 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); in vcn_v5_0_0_start()
942 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); in vcn_v5_0_0_stop_dpg_mode()
1118 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); in vcn_v5_0_0_unified_ring_get_wptr()
1139 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v5_0_0_unified_ring_set_wptr()
H A Dvcn_v4_0_5.c72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
970 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); in vcn_v4_0_5_start_dpg_mode()
973 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); in vcn_v4_0_5_start_dpg_mode()
974 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); in vcn_v4_0_5_start_dpg_mode()
1159 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); in vcn_v4_0_5_start()
1162 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); in vcn_v4_0_5_start()
1163 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); in vcn_v4_0_5_start()
1191 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); in vcn_v4_0_5_stop_dpg_mode()
1375 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); in vcn_v4_0_5_unified_ring_get_wptr()
1396 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v4_0_5_unified_ring_set_wptr()
H A Dvcn_v4_0.c72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
1067 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); in vcn_v4_0_start_dpg_mode()
1070 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); in vcn_v4_0_start_dpg_mode()
1071 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); in vcn_v4_0_start_dpg_mode()
1255 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); in vcn_v4_0_start()
1258 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); in vcn_v4_0_start()
1259 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); in vcn_v4_0_start()
1537 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); in vcn_v4_0_stop_dpg_mode()
1720 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); in vcn_v4_0_unified_ring_get_wptr()
1741 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v4_0_unified_ring_set_wptr()
H A Dvcn_v4_0_3.c65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
909 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); in vcn_v4_0_3_start_dpg_mode()
910 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); in vcn_v4_0_3_start_dpg_mode()
1276 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); in vcn_v4_0_3_start()
1282 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); in vcn_v4_0_3_start()
1310 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); in vcn_v4_0_3_stop_dpg_mode()
1461 regUVD_RB_WPTR); in vcn_v4_0_3_unified_ring_get_wptr()
1526 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, in vcn_v4_0_3_unified_ring_set_wptr()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1320 #define regUVD_RB_WPTR … macro
H A Dvcn_5_0_0_offset.h1120 #define regUVD_RB_WPTR … macro
H A Dvcn_4_0_5_offset.h1295 #define regUVD_RB_WPTR … macro
H A Dvcn_4_0_0_offset.h1340 #define regUVD_RB_WPTR … macro
H A Dvcn_4_0_3_offset.h1242 #define regUVD_RB_WPTR … macro