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Searched refs:regUVD_RB_RPTR (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
733 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); in vcn_v5_0_0_start_dpg_mode()
736 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); in vcn_v5_0_0_start_dpg_mode()
890 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); in vcn_v5_0_0_start()
893 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); in vcn_v5_0_0_start()
927 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v5_0_0_stop_dpg_mode()
1080 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); in vcn_v5_0_0_unified_ring_get_rptr()
H A Dvcn_v4_0_5.c71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
971 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); in vcn_v4_0_5_start_dpg_mode()
974 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); in vcn_v4_0_5_start_dpg_mode()
1158 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); in vcn_v4_0_5_start()
1161 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); in vcn_v4_0_5_start()
1192 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v4_0_5_stop_dpg_mode()
1353 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); in vcn_v4_0_5_unified_ring_get_rptr()
H A Dvcn_v4_0.c71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
1059 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); in vcn_v4_0_start_dpg_mode()
1062 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); in vcn_v4_0_start_dpg_mode()
1245 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); in vcn_v4_0_start()
1248 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); in vcn_v4_0_start()
1529 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v4_0_stop_dpg_mode()
1689 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); in vcn_v4_0_unified_ring_get_rptr()
H A Dvcn_v4_0_3.c64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
880 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); in vcn_v4_0_3_start_dpg_mode()
1243 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); in vcn_v4_0_3_start()
1279 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v4_0_3_stop_dpg_mode()
1406 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); in vcn_v4_0_3_unified_ring_get_rptr()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1318 #define regUVD_RB_RPTR … macro
H A Dvcn_5_0_0_offset.h1118 #define regUVD_RB_RPTR … macro
H A Dvcn_4_0_5_offset.h1293 #define regUVD_RB_RPTR … macro
H A Dvcn_4_0_0_offset.h1338 #define regUVD_RB_RPTR … macro
H A Dvcn_4_0_3_offset.h1240 #define regUVD_RB_RPTR … macro