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Searched refs:regUVD_POWER_STATUS (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
585 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v4_0_5_disable_static_power_gating()
590 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); in vcn_v4_0_5_disable_static_power_gating()
607 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v4_0_5_enable_static_power_gating()
610 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); in vcn_v4_0_5_enable_static_power_gating()
878 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, in vcn_v4_0_5_start_dpg_mode()
881 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); in vcn_v4_0_5_start_dpg_mode()
884 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); in vcn_v4_0_5_start_dpg_mode()
1187 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, in vcn_v4_0_5_stop_dpg_mode()
1194 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, in vcn_v4_0_5_stop_dpg_mode()
[all …]
H A Dvcn_v5_0_0.c41 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
567 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v5_0_0_disable_static_power_gating()
573 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); in vcn_v5_0_0_disable_static_power_gating()
591 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v5_0_0_enable_static_power_gating()
594 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); in vcn_v5_0_0_enable_static_power_gating()
683 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, in vcn_v5_0_0_start_dpg_mode()
687 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); in vcn_v5_0_0_start_dpg_mode()
690 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); in vcn_v5_0_0_start_dpg_mode()
938 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, in vcn_v5_0_0_stop_dpg_mode()
946 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, in vcn_v5_0_0_stop_dpg_mode()
[all …]
H A Dvcn_v4_0.c56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
642 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v4_0_disable_static_power_gating()
648 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); in vcn_v4_0_disable_static_power_gating()
667 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v4_0_enable_static_power_gating()
670 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); in vcn_v4_0_enable_static_power_gating()
973 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, in vcn_v4_0_start_dpg_mode()
976 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); in vcn_v4_0_start_dpg_mode()
979 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); in vcn_v4_0_start_dpg_mode()
1533 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, in vcn_v4_0_stop_dpg_mode()
1540 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, in vcn_v4_0_stop_dpg_mode()
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H A Dvcn_v5_0_1.c475 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, in vcn_v5_0_1_start_dpg_mode()
479 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); in vcn_v5_0_1_start_dpg_mode()
481 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); in vcn_v5_0_1_start_dpg_mode()
734 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, in vcn_v5_0_1_stop_dpg_mode()
742 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, in vcn_v5_0_1_stop_dpg_mode()
H A Dvcn_v4_0_3.c49 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
799 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, in vcn_v4_0_3_start_dpg_mode()
802 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); in vcn_v4_0_3_start_dpg_mode()
805 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); in vcn_v4_0_3_start_dpg_mode()
1306 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, in vcn_v4_0_3_stop_dpg_mode()
1313 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, in vcn_v4_0_3_stop_dpg_mode()
1317 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, in vcn_v4_0_3_stop_dpg_mode()
1820 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS); in vcn_v4_0_3_dump_ip_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1070 #define regUVD_POWER_STATUS … macro
H A Dvcn_5_0_0_offset.h946 #define regUVD_POWER_STATUS … macro
H A Dvcn_4_0_5_offset.h1119 #define regUVD_POWER_STATUS … macro
H A Dvcn_4_0_0_offset.h1150 #define regUVD_POWER_STATUS … macro
H A Dvcn_4_0_3_offset.h1066 #define regUVD_POWER_STATUS … macro