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Searched refs:regUVD_MASTINT_EN (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_1.c499 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); in vcn_v5_0_1_start_dpg_mode()
527 VCN, 0, regUVD_MASTINT_EN), in vcn_v5_0_1_start_dpg_mode()
600 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, in vcn_v5_0_1_start()
677 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), in vcn_v5_0_1_start()
H A Dvcn_v5_0_0.c703 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); in vcn_v5_0_0_start_dpg_mode()
731 VCN, inst_idx, regUVD_MASTINT_EN), in vcn_v5_0_0_start_dpg_mode()
808 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, in vcn_v5_0_0_start()
885 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), in vcn_v5_0_0_start()
H A Dvcn_v4_0_5.c901 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); in vcn_v4_0_5_start_dpg_mode()
953 VCN, inst_idx, regUVD_MASTINT_EN), in vcn_v4_0_5_start_dpg_mode()
1034 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, in vcn_v4_0_5_start()
1137 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), in vcn_v4_0_5_start()
H A Dvcn_v4_0_3.c830 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
884 VCN, 0, regUVD_MASTINT_EN), in vcn_v4_0_3_start_dpg_mode()
1152 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, in vcn_v4_0_3_start()
1249 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), in vcn_v4_0_3_start()
H A Dvcn_v4_0.c995 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); in vcn_v4_0_start_dpg_mode()
1049 VCN, inst_idx, regUVD_MASTINT_EN), in vcn_v4_0_start_dpg_mode()
1131 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, in vcn_v4_0_start()
1233 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), in vcn_v4_0_start()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1294 #define regUVD_MASTINT_EN … macro
H A Dvcn_5_0_0_offset.h166 #define regUVD_MASTINT_EN … macro
H A Dvcn_4_0_5_offset.h175 #define regUVD_MASTINT_EN … macro
H A Dvcn_4_0_0_offset.h188 #define regUVD_MASTINT_EN … macro
H A Dvcn_4_0_3_offset.h188 #define regUVD_MASTINT_EN … macro