Home
last modified time | relevance | path

Searched refs:regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c393 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v4_0_3_mc_resume()
402 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v4_0_3_mc_resume()
468 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v4_0_3_mc_resume_dpg_mode()
477 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
487 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v4_0_3_mc_resume_dpg_mode()
952 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v4_0_3_start_sriov()
963 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v4_0_3_start_sriov()
H A Dvcn_v5_0_0.c346 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v5_0_0_mc_resume()
353 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v5_0_0_mc_resume()
410 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v5_0_0_mc_resume_dpg_mode()
418 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
428 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v5_0_0_mc_resume_dpg_mode()
H A Dvcn_v4_0.c434 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v4_0_mc_resume()
441 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v4_0_mc_resume()
497 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v4_0_mc_resume_dpg_mode()
505 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
515 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v4_0_mc_resume_dpg_mode()
1344 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v4_0_start_sriov()
1355 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v4_0_start_sriov()
H A Dvcn_v4_0_5.c382 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v4_0_5_mc_resume()
389 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v4_0_5_mc_resume()
447 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v4_0_5_mc_resume_dpg_mode()
456 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
466 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v4_0_5_mc_resume_dpg_mode()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h232 #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH … macro
H A Dvcn_5_0_0_offset.h490 #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH … macro
H A Dvcn_4_0_5_offset.h575 #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH … macro
H A Dvcn_4_0_0_offset.h598 #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH … macro
H A Dvcn_4_0_3_offset.h600 #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH … macro