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Searched refs:regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c413 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v4_0_3_mc_resume()
508 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), in vcn_v4_0_3_mc_resume_dpg_mode()
516 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
979 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); in vcn_v4_0_3_start_sriov()
H A Dvcn_v5_0_0.c363 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v5_0_0_mc_resume()
449 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), in vcn_v5_0_0_mc_resume_dpg_mode()
457 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
H A Dvcn_v4_0_5.c399 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v4_0_5_mc_resume()
487 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), in vcn_v4_0_5_mc_resume_dpg_mode()
495 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
H A Dvcn_v4_0.c451 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v4_0_mc_resume()
536 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), in vcn_v4_0_mc_resume_dpg_mode()
544 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1372 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), in vcn_v4_0_start_sriov()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h304 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH … macro
H A Dvcn_5_0_0_offset.h558 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH … macro
H A Dvcn_4_0_5_offset.h647 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH … macro
H A Dvcn_4_0_0_offset.h670 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH … macro
H A Dvcn_4_0_3_offset.h672 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH … macro