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Searched refs:regUVD_LMI_CTRL (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c701 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v5_0_0_start_dpg_mode()
805 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); in vcn_v5_0_0_start()
806 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | in vcn_v5_0_0_start()
H A Dvcn_v4_0_5.c915 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v4_0_5_start_dpg_mode()
1047 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); in vcn_v4_0_5_start()
1048 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | in vcn_v4_0_5_start()
H A Dvcn_v4_0_3.c814 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
1133 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); in vcn_v4_0_3_start()
1134 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, in vcn_v4_0_3_start()
H A Dvcn_v4_0.c1000 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v4_0_start_dpg_mode()
1135 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); in vcn_v4_0_start()
1136 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | in vcn_v4_0_start()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h420 #define regUVD_LMI_CTRL … macro
H A Dvcn_5_0_0_offset.h636 #define regUVD_LMI_CTRL … macro
H A Dvcn_4_0_5_offset.h723 #define regUVD_LMI_CTRL … macro
H A Dvcn_4_0_0_offset.h748 #define regUVD_LMI_CTRL … macro
H A Dvcn_4_0_3_offset.h750 #define regUVD_LMI_CTRL … macro