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Searched refs:regUVD_JRBC_RB_WPTR (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v5_0_0.c373 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR, 0); in jpeg_v5_0_0_start_dpg_mode()
376 ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR); in jpeg_v5_0_0_start_dpg_mode()
450 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0); in jpeg_v5_0_0_start()
453 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); in jpeg_v5_0_0_start()
520 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); in jpeg_v5_0_0_dec_ring_get_wptr()
538 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v5_0_0_dec_ring_set_wptr()
H A Djpeg_v4_0_5.c448 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR, 0); in jpeg_v4_0_5_start_dpg_mode()
451 ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR); in jpeg_v4_0_5_start_dpg_mode()
533 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR, 0); in jpeg_v4_0_5_start()
536 ring->wptr = RREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR); in jpeg_v4_0_5_start()
608 return RREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_WPTR); in jpeg_v4_0_5_dec_ring_get_wptr()
626 WREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v4_0_5_dec_ring_set_wptr()
H A Djpeg_v5_0_1.c376 regUVD_JRBC_RB_WPTR, in jpeg_v5_0_1_start()
384 ring->wptr = RREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JRBC_RB_WPTR, in jpeg_v5_0_1_start()
448 return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_WPTR, in jpeg_v5_0_1_dec_ring_get_wptr()
468 regUVD_JRBC_RB_WPTR, in jpeg_v5_0_1_dec_ring_set_wptr()
H A Djpeg_v4_0.c406 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0); in jpeg_v4_0_start()
409 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); in jpeg_v4_0_start()
595 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); in jpeg_v4_0_dec_ring_get_wptr()
613 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v4_0_dec_ring_set_wptr()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h938 #define regUVD_JRBC_RB_WPTR … macro
H A Dvcn_5_0_0_offset.h742 #define regUVD_JRBC_RB_WPTR … macro
H A Dvcn_4_0_5_offset.h827 #define regUVD_JRBC_RB_WPTR … macro
H A Dvcn_4_0_0_offset.h858 #define regUVD_JRBC_RB_WPTR … macro