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Searched refs:regUVD_JRBC_RB_SIZE (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v5_0_0.c375 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v5_0_0_start_dpg_mode()
452 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v5_0_0_start()
H A Djpeg_v4_0.c408 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v4_0_start()
462 regUVD_JRBC_RB_SIZE), ring->ring_size / 4); in jpeg_v4_0_start_sriov()
H A Djpeg_v4_0_5.c450 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v4_0_5_start_dpg_mode()
535 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v4_0_5_start()
H A Djpeg_v5_0_1.c382 regUVD_JRBC_RB_SIZE, in jpeg_v5_0_1_start()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h972 #define regUVD_JRBC_RB_SIZE … macro
H A Dvcn_5_0_0_offset.h776 #define regUVD_JRBC_RB_SIZE … macro
H A Dvcn_4_0_5_offset.h861 #define regUVD_JRBC_RB_SIZE … macro
H A Dvcn_4_0_0_offset.h892 #define regUVD_JRBC_RB_SIZE … macro