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Searched refs:regUVD_IPX_DLDO_CONFIG (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c544 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); in vcn_v5_0_0_disable_static_power_gating()
549 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); in vcn_v5_0_0_disable_static_power_gating()
555 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); in vcn_v5_0_0_disable_static_power_gating()
561 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); in vcn_v5_0_0_disable_static_power_gating()
567 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); in vcn_v5_0_0_disable_static_power_gating()
572 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); in vcn_v5_0_0_disable_static_power_gating()
577 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); in vcn_v5_0_0_disable_static_power_gating()
582 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); in vcn_v5_0_0_disable_static_power_gating()
618 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); in vcn_v5_0_0_enable_static_power_gating()
624 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data); in vcn_v5_0_0_enable_static_power_gating()
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H A Dvcn_v4_0_5.c582 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, in vcn_v4_0_5_disable_static_power_gating()
586 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, in vcn_v4_0_5_disable_static_power_gating()
591 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, in vcn_v4_0_5_disable_static_power_gating()
596 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, in vcn_v4_0_5_disable_static_power_gating()
602 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, in vcn_v4_0_5_disable_static_power_gating()
606 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, in vcn_v4_0_5_disable_static_power_gating()
610 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, in vcn_v4_0_5_disable_static_power_gating()
614 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, in vcn_v4_0_5_disable_static_power_gating()
648 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, in vcn_v4_0_5_enable_static_power_gating()
653 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, in vcn_v4_0_5_enable_static_power_gating()
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H A Dumsch_mm_v4_0.c38 #define regUVD_IPX_DLDO_CONFIG 0x0064 macro
65 WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG, in umsch_mm_v4_0_load_microcode()
259 WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG, in umsch_mm_v4_0_ring_stop()
H A Djpeg_v4_0_5.c377 WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG), in jpeg_v4_0_5_disable_static_power_gating()
402 WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG), in jpeg_v4_0_5_enable_static_power_gating()
433 WREG32(SOC15_REG_OFFSET(JPEG, inst_idx, regUVD_IPX_DLDO_CONFIG), in jpeg_v4_0_5_start_dpg_mode()
H A Djpeg_v5_0_0.c274 WREG32_SOC15(JPEG, 0, regUVD_IPX_DLDO_CONFIG, data); in jpeg_v5_0_0_disable_power_gating()
293 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG), in jpeg_v5_0_0_enable_power_gating()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_5_0_0_offset.h942 #define regUVD_IPX_DLDO_CONFIG … macro
H A Dvcn_4_0_5_offset.h1241 #define regUVD_IPX_DLDO_CONFIG … macro