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Searched refs:regUVD_GFX10_ADDR_CONFIG (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_1.c428 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
623 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, in vcn_v5_0_1_start()
H A Dvcn_v5_0_0.c505 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
831 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, in vcn_v5_0_0_start()
H A Dvcn_v4_0_5.c530 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), in vcn_v4_0_5_mc_resume_dpg_mode()
1083 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, in vcn_v4_0_5_start()
H A Dvcn_v4_0_3.c582 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
1203 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, in vcn_v4_0_3_start()
H A Dvcn_v4_0.c585 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1180 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, in vcn_v4_0_start()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1134 #define regUVD_GFX10_ADDR_CONFIG … macro
H A Dvcn_5_0_0_offset.h1036 #define regUVD_GFX10_ADDR_CONFIG … macro
H A Dvcn_4_0_5_offset.h1205 #define regUVD_GFX10_ADDR_CONFIG … macro
H A Dvcn_4_0_0_offset.h1214 #define regUVD_GFX10_ADDR_CONFIG … macro
H A Dvcn_4_0_3_offset.h1160 #define regUVD_GFX10_ADDR_CONFIG … macro