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Searched refs:regUVD_DPG_PAUSE (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)
1038 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & in vcn_v5_0_0_pause_dpg_mode()
1048 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); in vcn_v5_0_0_pause_dpg_mode()
1051 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, in vcn_v5_0_0_pause_dpg_mode()
1058 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); in vcn_v5_0_0_pause_dpg_mode()
H A Dvcn_v4_0_5.c88 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)
1307 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & in vcn_v4_0_5_pause_dpg_mode()
1317 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); in vcn_v4_0_5_pause_dpg_mode()
1320 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, in vcn_v4_0_5_pause_dpg_mode()
1331 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); in vcn_v4_0_5_pause_dpg_mode()
H A Dvcn_v4_0.c88 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)
1644 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & in vcn_v4_0_pause_dpg_mode()
1654 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); in vcn_v4_0_pause_dpg_mode()
1657 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, in vcn_v4_0_pause_dpg_mode()
1667 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); in vcn_v4_0_pause_dpg_mode()
H A Dvcn_v4_0_3.c81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1086 #define regUVD_DPG_PAUSE … macro
H A Dvcn_5_0_0_offset.h966 #define regUVD_DPG_PAUSE … macro
H A Dvcn_4_0_5_offset.h1139 #define regUVD_DPG_PAUSE … macro
H A Dvcn_4_0_0_offset.h1166 #define regUVD_DPG_PAUSE … macro
H A Dvcn_4_0_3_offset.h1090 #define regUVD_DPG_PAUSE … macro