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Searched refs:regUVD_DPG_LMA_DATA (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_jpeg.h67 regUVD_DPG_LMA_DATA, value); \
86 RREG32_SOC15(JPEG, inst_idx, regUVD_DPG_LMA_DATA); \
H A Damdgpu_vcn.h200 regUVD_DPG_LMA_DATA, value); \
H A Dvcn_v4_0_5.c44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA
86 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
H A Djpeg_v4_0_5.c39 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA
H A Dvcn_v4_0_3.c42 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA
79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
H A Dvcn_v4_0.c44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA
86 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
H A Dvcn_v5_0_0.c69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1082 #define regUVD_DPG_LMA_DATA … macro
H A Dvcn_5_0_0_offset.h962 #define regUVD_DPG_LMA_DATA … macro
H A Dvcn_4_0_5_offset.h1135 #define regUVD_DPG_LMA_DATA … macro
H A Dvcn_4_0_0_offset.h1162 #define regUVD_DPG_LMA_DATA … macro
H A Dvcn_4_0_3_offset.h1086 #define regUVD_DPG_LMA_DATA … macro