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Searched refs:regUVD_DPG_LMA_CTL (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_jpeg.h72 regUVD_DPG_LMA_CTL, \
83 regUVD_DPG_LMA_CTL, \
H A Damdgpu_vcn.h203 regUVD_DPG_LMA_CTL, \
H A Dvcn_v4_0_5.c42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL
85 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
H A Djpeg_v4_0_5.c37 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL
H A Dvcn_v4_0_3.c40 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL
78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
H A Dvcn_v4_0.c42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL
85 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
H A Dvcn_v5_0_0.c68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1080 #define regUVD_DPG_LMA_CTL … macro
H A Dvcn_5_0_0_offset.h960 #define regUVD_DPG_LMA_CTL … macro
H A Dvcn_4_0_5_offset.h1133 #define regUVD_DPG_LMA_CTL … macro
H A Dvcn_4_0_0_offset.h1160 #define regUVD_DPG_LMA_CTL … macro
H A Dvcn_4_0_3_offset.h1084 #define regUVD_DPG_LMA_CTL … macro