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Searched refs:regUVD_CGC_GATE (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c659 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); in vcn_v4_0_5_disable_clock_gating()
681 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); in vcn_v4_0_5_disable_clock_gating()
682 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v4_0_5_disable_clock_gating()
794 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v4_0_5_disable_clock_gating_dpg_mode()
H A Dvcn_v4_0_3.c582 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE); in vcn_v4_0_3_disable_clock_gating()
596 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE, data); in vcn_v4_0_3_disable_clock_gating()
597 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v4_0_3_disable_clock_gating()
690 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
H A Dvcn_v4_0.c723 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); in vcn_v4_0_disable_clock_gating()
745 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); in vcn_v4_0_disable_clock_gating()
746 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v4_0_disable_clock_gating()
858 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1244 #define regUVD_CGC_GATE … macro
H A Dvcn_5_0_0_offset.h32 #define regUVD_CGC_GATE … macro
H A Dvcn_4_0_5_offset.h31 #define regUVD_CGC_GATE … macro
H A Dvcn_4_0_0_offset.h32 #define regUVD_CGC_GATE … macro
H A Dvcn_4_0_3_offset.h32 #define regUVD_CGC_GATE … macro