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Searched refs:regUVD_CGC_CTRL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c651 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
655 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_5_disable_clock_gating()
682 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
703 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_5_disable_clock_gating()
788 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_5_disable_clock_gating_dpg_mode()
819 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_enable_clock_gating()
823 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_5_enable_clock_gating()
825 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_enable_clock_gating()
846 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_5_enable_clock_gating()
H A Dvcn_v4_0_3.c604 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_disable_clock_gating()
608 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_disable_clock_gating()
627 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_disable_clock_gating()
640 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_disable_clock_gating()
714 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
748 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_enable_clock_gating()
752 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_enable_clock_gating()
754 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_enable_clock_gating()
766 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_enable_clock_gating()
H A Dvcn_v4_0.c724 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_disable_clock_gating()
728 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_disable_clock_gating()
755 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_disable_clock_gating()
776 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_disable_clock_gating()
861 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
892 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_enable_clock_gating()
896 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_enable_clock_gating()
898 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_enable_clock_gating()
919 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_enable_clock_gating()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1248 #define regUVD_CGC_CTRL … macro
H A Dvcn_5_0_0_offset.h34 #define regUVD_CGC_CTRL … macro
H A Dvcn_4_0_5_offset.h33 #define regUVD_CGC_CTRL … macro
H A Dvcn_4_0_0_offset.h34 #define regUVD_CGC_CTRL … macro
H A Dvcn_4_0_3_offset.h34 #define regUVD_CGC_CTRL … macro