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Searched refs:regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h6249 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX macro
H A Ddpcs_4_2_3_offset.h618 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX macro
H A Ddpcs_4_2_2_offset.h582 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX macro
H A Ddpcs_4_2_0_offset.h585 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h10942 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX macro
H A Ddcn_3_1_5_offset.h11539 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX macro
H A Ddcn_3_5_1_offset.h9769 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX macro
H A Ddcn_3_5_0_offset.h9790 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX macro
H A Ddcn_3_1_4_offset.h10901 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX macro
H A Ddcn_3_1_2_offset.h11794 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX macro
H A Ddcn_3_2_1_offset.h10947 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX macro
H A Ddcn_3_1_6_offset.h12022 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX macro
H A Ddcn_4_1_0_offset.h11190 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX macro