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Searched refs:regSQ_IND_INDEX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c717 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, in wave_read_ind()
729 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, in wave_read_regs()
1628 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)},
H A Dgfx_v12_1.c756 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, in wave_read_ind()
767 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, in wave_read_regs()
H A Dgfx_v12_0.c826 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_ind()
836 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_regs()
H A Dgfx_v11_0.c997 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_ind()
1007 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_regs()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h496 #define regSQ_IND_INDEX … macro
H A Dgc_9_4_2_offset.h6186 #define regSQ_IND_INDEX … macro
H A Dgc_12_0_0_offset.h7311 #define regSQ_IND_INDEX … macro
H A Dgc_11_0_3_offset.h2232 #define regSQ_IND_INDEX … macro
H A Dgc_11_0_0_offset.h2166 #define regSQ_IND_INDEX … macro