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Searched refs:regSPI_WCL_PIPE_PERCENT_CS0 (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3164 #define regSPI_WCL_PIPE_PERCENT_CS0 … macro
H A Dgc_9_4_2_offset.h5990 #define regSPI_WCL_PIPE_PERCENT_CS0 … macro
H A Dgc_11_5_0_offset.h3539 #define regSPI_WCL_PIPE_PERCENT_CS0 … macro
H A Dgc_12_0_0_offset.h8007 #define regSPI_WCL_PIPE_PERCENT_CS0 … macro
H A Dgc_11_0_3_offset.h4790 #define regSPI_WCL_PIPE_PERCENT_CS0 … macro
H A Dgc_11_0_0_offset.h4566 #define regSPI_WCL_PIPE_PERCENT_CS0 … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c3430 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); in gfx_v9_4_3_emit_wave_limit_cs()