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Searched refs:regSPI_GDBG_PER_VMID_CNTL (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_2.c767 WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_PER_VMID_CNTL), data); in gfx_v9_4_2_debug_trap_config_init()
H A Dgfx_v9_4_3.c1264 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); in gfx_v9_4_3_xcc_init_compute_vmid()
1266 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); in gfx_v9_4_3_xcc_init_compute_vmid()
H A Dgfx_v12_0.c1690 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); in gfx_v12_0_init_compute_vmid()
1692 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); in gfx_v12_0_init_compute_vmid()
H A Dgfx_v11_0.c1951 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); in gfx_v11_0_init_compute_vmid()
1953 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); in gfx_v11_0_init_compute_vmid()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3184 #define regSPI_GDBG_PER_VMID_CNTL macro
H A Dgc_9_4_2_offset.h6010 #define regSPI_GDBG_PER_VMID_CNTL macro
H A Dgc_11_5_0_offset.h3557 #define regSPI_GDBG_PER_VMID_CNTL macro
H A Dgc_12_0_0_offset.h8025 #define regSPI_GDBG_PER_VMID_CNTL macro
H A Dgc_11_0_3_offset.h4808 #define regSPI_GDBG_PER_VMID_CNTL macro
H A Dgc_11_0_0_offset.h4584 #define regSPI_GDBG_PER_VMID_CNTL macro