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Searched refs:regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h867 #define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX … macro
H A Dgc_9_4_2_offset.h5935 #define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX … macro
H A Dgc_11_5_0_offset.h1344 #define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX … macro
H A Dgc_12_0_0_offset.h7462 #define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX … macro
H A Dgc_11_0_3_offset.h2349 #define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX … macro
H A Dgc_11_0_0_offset.h2255 #define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX … macro