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Searched refs:regSPI_COMPUTE_QUEUE_RESET (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c413 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); in mes_v11_0_reset_queue_mmio()
H A Dgfx_v11_0.c4800 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); in gfx_v11_0_soft_reset()
6599 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); in gfx_v11_0_reset_kcq()
H A Dgfx_v9_4_3.c300 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); in gfx_v9_4_3_kiq_reset_hw_queue()
H A Dgfx_v12_0.c5223 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); in gfx_v12_0_reset_kcq()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3194 #define regSPI_COMPUTE_QUEUE_RESET macro
H A Dgc_9_4_2_offset.h6018 #define regSPI_COMPUTE_QUEUE_RESET macro
H A Dgc_11_5_0_offset.h3559 #define regSPI_COMPUTE_QUEUE_RESET macro
H A Dgc_12_0_0_offset.h8027 #define regSPI_COMPUTE_QUEUE_RESET macro
H A Dgc_11_0_3_offset.h4810 #define regSPI_COMPUTE_QUEUE_RESET macro
H A Dgc_11_0_0_offset.h4586 #define regSPI_COMPUTE_QUEUE_RESET macro