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Searched refs:regSH_MEM_CONFIG (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v11.c86 WREG32(SOC15_REG_OFFSET(GC, 0, regSH_MEM_CONFIG), sh_mem_config); in program_sh_mem_settings_v11()
H A Dgfx_v12_1.c1427 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v12_1_xcc_init_compute_vmid()
1466 regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v12_1_xcc_constants_init()
H A Dgfx_v12_0.c1792 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v12_0_init_compute_vmid()
1832 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v12_0_constants_init()
H A Dgfx_v11_0.c2097 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v11_0_init_compute_vmid()
2178 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v11_0_constants_init()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h424 #define regSH_MEM_CONFIG … macro
H A Dgc_9_4_2_offset.h6118 #define regSH_MEM_CONFIG … macro
H A Dgc_12_0_0_offset.h9261 #define regSH_MEM_CONFIG … macro
H A Dgc_11_0_3_offset.h6564 #define regSH_MEM_CONFIG … macro
H A Dgc_11_0_0_offset.h6284 #define regSH_MEM_CONFIG … macro